Rose Thompson
a8ab3c8342
Ok that is a stange bug.
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The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
2023-12-20 12:25:34 -06:00
Rose Thompson
9ee1ffe8fe
Almost working with modelsim and verilator.
2023-12-20 11:29:31 -06:00
Rose Thompson
4f59bd492d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-12-19 12:06:04 -06:00
Rose Thompson
2e792606dd
More progress. Most tests are passing in modelsim.
2023-12-19 12:06:00 -06:00
Rose Thompson
74238defc3
Progress.
2023-12-18 20:23:19 -06:00
David Harris
6186181d46
Merge pull request #537 from ross144/main
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Almost having working Verilator. One issue in the testbench remains.
2023-12-18 18:13:56 -08:00
Rose Thompson
1e1759c258
Restored the one hack change which prevents verilator from working.
2023-12-18 17:00:53 -06:00
Rose Thompson
408bb2c35b
Yay! I got verilator to compile our testbench! Does it actually work I don't know.
2023-12-18 16:44:34 -06:00
Rose Thompson
0f7b6ada04
Cleanup.
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Verilator still has issues with riscassertions.sv and the testbench
2023-12-18 16:38:56 -06:00
Rose Thompson
b7b245fe2f
functionName.sv is now linting for rv64gc.
2023-12-18 16:37:26 -06:00
Rose Thompson
c1ac153a4f
Closer to verilator support.
2023-12-18 16:26:56 -06:00
Rose Thompson
58942b246b
Kind of a frustrating set of changes to get the verilator errors out of the copyShadow module.
2023-12-18 13:34:14 -06:00
Rose Thompson
4a3cc8b9c8
More progress towards verilator.
2023-12-18 13:26:43 -06:00
Rose Thompson
5062a8c89c
Added parameter for cache's SRAM length.
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Progress towards verilator support.
2023-12-18 12:50:49 -06:00
James E. Stine
f4c1713ed4
Fix issue with running all and then going from one operand width to another. Issue is due to signals resolving between sizes. I did not catch it before because I did not run through the complete exhaustive tests. This time, went through all tests and tested all the data sizes.
2023-12-17 20:55:06 -06:00
James E. Stine
8d8bad61d4
Fix to take care of Issue #507 . Issue was caused with time delay in testbench-fp.sv that interfered with the if statement in the DIVSQRT condition for generating a vector. This original time delay was given to guarantee that the previous operation would complete. However, the testbench was modified to make sure this would not happen and this time delay is not needed obviating any issue that caused Issue #507 . Some other small enhancements were made to the testbench-fp.sv for beautification, as well. A full test was run on the testbench to check its validity.
2023-12-15 17:02:11 -06:00
David Harris
68d96a929c
Fixed hierarchical path to EcallFaultM in testbench
2023-12-13 16:37:54 -08:00
David Harris
ff26baf7e8
Rolled back attempt to support Verilator
2023-12-13 12:53:44 -08:00
David Harris
aff61ea97a
Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator
2023-12-13 11:33:59 -08:00
David Harris
b268a3b9d3
Added SPI support to Imperas testbenches
2023-12-07 09:44:31 -08:00
David Harris
c0801263f1
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-11-23 20:43:22 -08:00
David Harris
bcc20c6bd5
Merge pull request #505 from stineje/main
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Update fix for cvtint testbench-fp
2023-11-23 20:43:00 -08:00
David Harris
3df4c13daa
Updated wallyTracer for Linux boot and wally-batch.do to remove buildroot checkpoint support
2023-11-23 20:36:45 -08:00
David Harris
1f57df7f8b
Fixed reference to deleted atomic signal in cache
2023-11-23 20:29:10 -08:00
James E. Stine
1ab7522064
Update fix for cvtint testbench-fp
2023-11-23 17:56:51 -06:00
Rose Thompson
1dac4d221e
Disable the trace for normal operation.
2023-11-21 13:49:07 -06:00
Rose Thompson
c77a47b403
Output the instruction trace to the logs directory.
2023-11-21 13:47:58 -06:00
Rose Thompson
b02bd6c835
Finally we got the wally tracer working with linux.
2023-11-21 13:45:55 -06:00
Rose Thompson
3fd6d3464c
We are logging now.
2023-11-21 13:02:34 -06:00
Rose Thompson
6ff8d19157
Added code to the wallyTracer to support outputing an instruction trace.
2023-11-21 12:28:19 -06:00
Jacob Pease
a1e7158bd9
Merge branch 'main' of github.com:openhwgroup/cvw
2023-11-18 19:20:48 -06:00
David Harris
8baa5b2e7b
Merge pull request #483 from ross144/main
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Fixed branch predictor embench generation results
2023-11-17 10:07:30 -08:00
Rose Thompson
38b327eaf8
Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters.
2023-11-17 11:21:25 -06:00
Jacob Pease
23e5fca2a7
Merge branch 'main' of github.com:jacobpease/cvw
2023-11-16 14:04:11 -06:00
David Harris
94201e993f
Merge pull request #481 from ross144/main
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Fixed the BTB logger so sim_bp correctly reports BTB performance
2023-11-15 17:45:38 -08:00
Rose Thompson
bc935b1b3b
Fixed second bug in the logger script when branch logging enabled but counter logger not.
2023-11-15 14:56:02 -06:00
Rose Thompson
5d4a89b27c
Fixed bug in the btb branch logging.
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We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
2023-11-15 14:51:47 -06:00
David Harris
cfaeeae25a
Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter
2023-11-15 08:15:01 -08:00
Rose Thompson
feb45b9b59
Patched up linux imperas testbench.
2023-11-14 14:20:13 -06:00
Rose Thompson
efc1d732d8
Fixed the imperas testbench to be compatible with the config changes.
2023-11-14 12:57:44 -06:00
David Harris
a77bea9954
Merge pull request #472 from ross144/main
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Merge Zicclsm into main branch and removes the FPGA config. FPGA makefile now automatically creates the config when building
2023-11-14 08:34:06 -08:00
Rose Thompson
95fc5f4a1c
Towards removing the FPGA config file.
2023-11-13 17:20:26 -06:00
Rose Thompson
da59cb71a9
Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.
2023-11-13 14:12:27 -06:00
Rose Thompson
540d8d930d
Cleanup.
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Linux makefile
wally tracer. probably reduce some complexity here.
2023-11-13 14:04:43 -06:00
David Harris
6ac83c776e
Cleaned up number of bits in fdivsqrt
2023-11-11 15:50:06 -08:00
David Harris
2bf5143163
Bug fixes related to size of fpdivsqrt bit count and number of cycles
2023-11-11 05:58:53 -08:00
David Harris
448ced00c5
Fixed testbench-fp to reflect signal name changes
2023-11-11 04:05:34 -08:00
Rose Thompson
b74bfbeefd
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
Rose Thompson
baacb6f6eb
Missed tests.vh.
2023-11-10 16:10:10 -06:00
David Harris
bddd2d573e
Shortened path to PCSrcE in logger to avoid problematic hierarchical reference
2023-11-05 07:06:53 -08:00
