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156 Commits

Author SHA1 Message Date
Ross Thompson
9b959715a0 removed mmustall and finished port annotations on ptw and lsuArb. 2021-07-03 16:06:09 -05:00
Ross Thompson
fd088f8ecd Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser. 2021-07-03 15:51:25 -05:00
Ross Thompson
46831035fb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-02 13:56:49 -05:00
Ross Thompson
549b7b2a62 Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
David Harris
1ce98cc100 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-02 12:52:20 -04:00
David Harris
648c09e5ef Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:04:13 -04:00
Ross Thompson
386193de00 added page table walker fault exit for icache. 2021-07-01 17:59:55 -05:00
Ross Thompson
b31e0afc2a The icache now correctly interlocks with the PTW on TLB miss. 2021-06-30 11:24:26 -05:00
Ross Thompson
2598f08782 Page table walker now walks the table. 
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
 2021-06-29 22:33:57 -05:00
Katherine Parry
6216bd7172 FPU control signals changed and FMA works 2021-06-28 18:53:58 -04:00
Ross Thompson
ae6140bd94 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
bbracker
aa8da43743 temporarily disable PMP checking for EBU accesses. 2021-06-26 07:19:51 -04:00
Ross Thompson
a4266c0136 Some progress. Had to change how the page table walker got it's ready. 2021-06-25 15:07:41 -05:00
bbracker
4e09793a9a ah merge; I checked and this does pass all of regression except lints 2021-06-25 07:37:06 -04:00
Kip Macsai-Goren
1485d29dde Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR. 2021-06-24 20:01:11 -04:00
Katherine Parry
bc8d660bc5 FPU forwarding reworked pt.1 2021-06-24 18:39:18 -04:00
bbracker
ced5039776 Revert "fixed forwarding" 
This reverts commit 0f4a4a6ade.
 2021-06-24 17:39:37 -04:00
Ross Thompson
0377d3b2c9 Progress. 2021-06-24 13:05:22 -05:00
bbracker
0f4a4a6ade fixed forwarding 2021-06-24 11:20:21 -04:00
Kip Macsai-Goren
547bf1d0af added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day. 2021-06-23 19:59:06 -04:00
Ross Thompson
6134c22aca Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two. 
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
 2021-06-23 16:43:22 -05:00
Ross Thompson
d5063bee7d Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache. 2021-06-23 15:13:56 -05:00
David Harris
1972d83002 Refactored pmachecker to have adrdecs used in uncore 2021-06-23 01:41:00 -04:00
David Harris
6dc54acde8 renamed dmem to lsu and removed adrdec module from pmpadrdec 2021-06-22 23:03:43 -04:00
bbracker
ae0fa90450 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-22 18:28:30 -04:00
bbracker
b43a8885cd give EBU a dedicated PMA unit as just an address decoder 2021-06-22 18:28:08 -04:00
Katherine Parry
9eb6eb40bf rv64f FLW passes imperas tests 2021-06-22 16:36:16 -04:00
David Harris
aef408af58 Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
David Harris
21a55458ca Made MemPAdrM and related signals PA_BITS wide 2021-06-18 09:36:22 -04:00
David Harris
e03912f64c Cleaned up name of MTIME register in CSRC 2021-06-18 07:53:49 -04:00
bbracker
7d1469a06c provide time and timeh CSRs based on CLINT's counter 2021-06-17 08:38:30 -04:00
David Harris
9a17556de4 Start to parameterize number of PMP Entries 2021-06-08 15:29:22 -04:00
bbracker
17960a6484 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine 2021-06-08 12:41:25 -04:00
bbracker
5026a42fac * GPIO comprehensive testing 
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
 2021-06-08 12:32:46 -04:00
David Harris
1e67db2f0c Second attept to commit refactoring config files 2021-06-07 12:37:46 -04:00
Katherine Parry
e4db6ea6f5 fixed lint warnings for fpu and lzd 2021-06-05 12:06:33 -04:00
Kip Macsai-Goren
d69501c4fa Cleaned up some unused signals 2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
7e41b17e65 restructured so that pma/pmp are a part of mmu 2021-06-04 17:05:07 -04:00
bbracker
28abd28b1f fixed InstrValid signals and implemented less costly MEPC loading 2021-06-02 10:03:19 -04:00
bbracker
a45b61ede9 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) 2021-05-28 23:11:37 -04:00
Katherine Parry
65eca433b6 All compare instructions pass imperas tests 2021-05-27 15:23:28 -04:00
Katherine Parry
3869a73a9c renamed top level FPU wires 2021-05-25 20:04:34 -04:00
Katherine Parry
03aea055fa FMV.X.D imperas test passes 2021-05-24 14:44:30 -04:00
Katherine Parry
55f22979ca FSD and FLD imperas tests pass 2021-05-23 18:33:14 -04:00
Katherine Parry
71e4a10efb FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
Katherine Parry
409438bc95 floating point infinite loop removed from imperas tests 2021-05-18 10:42:51 -04:00
Thomas Fleming
1fc607b399 Remove busy-mmu and fix missing signal 2021-05-14 07:14:20 -04:00
Thomas Fleming
94d734cca9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-05-03 14:02:19 -04:00
Katherine Parry
9252d08b41 fpu imperas tests run 2021-05-01 02:18:01 +00:00
Thomas Fleming
e091f430e0 Clean up PMA checker and begin PMP checker 2021-04-29 02:20:39 -04:00
Ross Thompson
9e40fb072c Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
Ross Thompson
d7fea1ba3c almost working icache. 2021-04-23 16:47:23 -05:00
Ross Thompson
c9bdaceddb Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Thomas Fleming
e7822ce20c Implement first pass at the PMA checker 2021-04-22 15:34:02 -04:00
Thomas Fleming
4d4ca24640 Extend stall on leaf page lookups 2021-04-22 01:51:38 -04:00
Thomas Fleming
70c801331a Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Jarred Allen
757b64e487 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
Thomas Fleming
ae888b5705 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
f0c926cf68 Move InstrPageFault to fetch stage 2021-04-13 13:39:22 -04:00
Teo Ene
0bffac2c74 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Jarred Allen
6ce4d44ae1 Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
d901cfc848 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Thomas Fleming
5946b860ca Comment out fpu from hart until module exists 2021-04-03 22:34:11 -04:00
Thomas Fleming
8f31e00f6a Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
e04ad8f304 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Katherine Parry
08b31f7b2a Integrated FPU 2021-04-03 20:52:26 +00:00
James E. Stine
9026357350 Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Ross Thompson
f1107c5d7b Corrected a number of bugs in the branch predictor. 
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
 2021-03-31 11:54:02 -05:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Jarred Allen
fdecd6c56c Clean up some stuff 2021-03-25 13:04:54 -04:00
Jarred Allen
e8e4e1bee2 rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
2f5d854f87 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/uncore/dtim.sv
 2021-03-25 12:10:26 -04:00
Thomas Fleming
89a2fe5741 Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Jarred Allen
1f01a12be9 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Shreya Sanghai
09b90557f7 PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
50c961bbe4 Merge changes from main 2021-03-18 18:58:10 -04:00
Thomas Fleming
062c4d40da Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Jarred Allen
003242ae8a Merge upstream changes 2021-03-14 14:57:53 -04:00
Thomas Fleming
e57b6cf18c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
David Harris
fe4d288589 Initial untested implementation of AMO instructions 2021-03-11 00:11:31 -05:00
Jarred Allen
c0ee17b6ac Merge upstream changes 2021-03-09 21:20:34 -05:00
Thomas Fleming
97e9baa316 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
e48dc38869 Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Jarred Allen
5da98b5381 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Ross Thompson
619bbd9d83 Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Thomas Fleming
8c410b6fbe Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5 Install tlb into ifu 2021-03-04 03:11:34 -05:00
David Harris
6f4e8b723e Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
Ross Thompson
6191fcb1af Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
David Harris
73920282af Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
David Harris
0258901865 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
David Harris
cd4ba8831c Merged bus into main 2021-02-25 00:28:41 -05:00
David Harris
38b8cc652c All tests passing with bus interface 2021-02-24 07:25:03 -05:00
Ross Thompson
c856003f73 RAS needs to be reset or preloaded. For now I just reset it. 
Fixed bug with the instruction class.
Most tests now pass.  Only Wally-JAL and the compressed instruction tests fail.  Currently the bpred does not support compressed.  This will be in the next version.
 2021-02-19 20:09:07 -06:00
Ross Thompson
bbe0db3ebe Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
David Harris
adc5d5bc1a Added MUL 2021-02-15 22:27:35 -05:00
David Harris
842c374de9 Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
33110ed636 Data memory bus integration 2021-02-07 23:21:55 -05:00