Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-31 00:44:38 +00:00
Code Issues Packages Projects Releases Wiki Activity
1,218 Commits 4 Branches 2 Tags 53 MiB
eb948f81dc
Commit Graph

63 Commits

Author SHA1 Message Date
Ross Thompson
71a23626d5 Fixed bug in the LSU pagetable walker interlock. 2021-07-06 10:41:36 -05:00
Ross Thompson
f2c4df0a5b Removed the TranslationVAdrQ as it is not necessary. 2021-07-04 16:49:34 -05:00
Ross Thompson
8ae0a5bd7d relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic. 2021-07-04 13:49:38 -05:00
Ross Thompson
3dae02818c OMG. It's working! 2021-07-01 17:37:53 -05:00
Ross Thompson
c3eaa3169e Fixed the wrong virtual address write into the dtlb. 2021-07-01 16:55:16 -05:00
Ross Thompson
9d9415ea67 Got some stores working in virtual memory. 2021-07-01 12:49:09 -05:00
Ross Thompson
4530e43df6 The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay. 2021-06-30 17:02:36 -05:00
Ross Thompson
07a0b66fdf Major rewrite of ptw to remove combo loop. 2021-06-30 16:25:03 -05:00
Ross Thompson
b31e0afc2a The icache now correctly interlocks with the PTW on TLB miss. 2021-06-30 11:24:26 -05:00
Ross Thompson
2598f08782 Page table walker now walks the table. 
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
 2021-06-29 22:33:57 -05:00
Ross Thompson
ae6140bd94 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
Ross Thompson
8dfbf60b67 AMO and LR/SC instructions now working correctly. 
Page table walking is not working.
 2021-06-25 15:42:07 -05:00
Ross Thompson
9fd1761fd6 Working through a combo loop. 2021-06-25 14:49:27 -05:00
Ross Thompson
17636b3293 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
Ross Thompson
d8183e59e4 Works until pma checker breaks the simulation by reading HADDR rather than data physical address. 2021-06-24 14:42:59 -05:00
Ross Thompson
e200b4b5a4 Continued I-Cache cleanup. 
Removed strange mux on InstrRawD along with
the select logic.
 2021-06-04 15:14:05 -05:00
Ross Thompson
35afdecda2 Moved I-Cache offset selection mux to icache.sv (top level). 
When we switch to set associative this is will be more efficient.
 2021-06-04 13:49:33 -05:00
Ross Thompson
2c16591396 Reorganized the icache names. 2021-06-04 12:53:42 -05:00
Ross Thompson
ed4f2ecb24 fixed subtle typo in icache fsm. Was messing up hit spill hit. 
I believe the mibench qsort benchmark runs after this icache fix.
 2021-05-03 16:55:36 -05:00
Ross Thompson
7185905f7b Reduced icache to 1 port memory. 2021-05-03 14:47:49 -05:00
Ross Thompson
12b978fec2 Eliminated extra register and fixed ports to icache. 
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
 2021-05-03 12:04:54 -05:00
Ross Thompson
fdf4954a20 Added back in function name to wave.do 2021-05-03 09:04:48 -05:00
Ross Thompson
14a69c1d06 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Ross Thompson
9e40fb072c Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
Ross Thompson
d7fea1ba3c almost working icache. 2021-04-23 16:47:23 -05:00
Ross Thompson
c9bdaceddb Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Ross Thompson
04eb302925 Yes. The hack to not repeat the d memory operation fixed this issue. 2021-04-22 15:22:56 -05:00
Ross Thompson
7c8d2e9b78 Partially working icache. 
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory.  This keeps StallF high and
the icache FSM is never allowed to complete.
 2021-04-22 10:20:36 -05:00
Ross Thompson
50e893eec9 Fixed for the instruction spills. 2021-04-21 16:47:05 -05:00
Ross Thompson
269ea7997c major progress. 
It's running the icache is imperas tests now.
Compressed does not work yet.
 2021-04-21 08:39:54 -05:00
Ross Thompson
a861a37b72 Why was the linter messed up? 
There are a number of combo loops which need fixing outside the icache.  They may be fixed in main.
We get to instruction address 50 now!
 2021-04-20 22:06:12 -05:00
Ross Thompson
daa1ab9261 Progress on icache. Fixed some issues aligning the PC with instruction. Still broken. 2021-04-20 21:19:53 -05:00
Ross Thompson
649589ee2c Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Ross Thompson
75b97f1422 Created special test for driving the instruction spill error. 
The extact problem occurs when a 4 byte instruction startles two cache blocks (or without a cache two ahbi words) and the code jumps to a cache block other than the next cache block. Consider the following sample of code.

0000000000000080 <test_spill>:
  80:	42a9                	li	t0,10
  82:	0001                	nop
  84:	0001                	nop
  86:	0001                	nop
  88:	02bd                	addi	t0,t0,15
  8a:	00628e33          	add	t3,t0,t1
  8e:	01ce8963          	beq	t4,t3,a0 <match>

0000000000000092 <failure>:
  92:	557d                	li	a0,-1
  94:	8082                	ret
  96:	00000013          	nop
  9a:	00000013          	nop
  9e:	0001                	nop

00000000000000a0 <match>:
  a0:	1ffd                	addi	t6,t6,-1
  a2:	fc0f9fe3          	bnez	t6,80 <test_spill>
  a6:	4501                	li	a0,0
  a8:	8082                	ret

Instructions 0x88, 0x8a and 0x8e are read incorrectly.  However once the branch predictor begins to correctly predict the beq at 0x8e the instrution at 0xa0 is loaded incorrectly as the 2 upper bytes of 0x8e and the two bytes of 0x92.  This amalgamation causes c.addi at 0xa0 to do something else and the loop never terminates.

The button of wavefile wave.do shows the exact problem in the 'icache'.
 2021-04-08 15:05:08 -05:00
Ross Thompson
7f12c7af90 Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
Ross Thompson
d901cfc848 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
0a20e33971 Steps to getting branch predictor benchmarks running. 2021-04-06 21:20:51 -05:00
Ross Thompson
a743acd1fd Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
Ross Thompson
1e83810450 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
ShreyaSanghai
da4086db79 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Ross Thompson
cdb7d15709 Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions. 2021-03-24 15:56:55 -05:00
Ross Thompson
a768c0406c Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed. 2021-03-24 13:03:43 -05:00
Ross Thompson
ace39940b4 Fixed RAS errors. Still some room for improvement with the BTB and RAS. 2021-03-23 23:00:44 -05:00
Ross Thompson
72d25d4443 Fixed a bunch of bugs with the RAS. 2021-03-23 21:49:16 -05:00
Ross Thompson
9d5c351340 fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle. 2021-03-23 20:06:45 -05:00
Ross Thompson
dee5d16850 fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled. 2021-03-23 16:53:48 -05:00
Ross Thompson
4836e8fe2c Simulation definitely shows the branch predictor counters and branch predictor don't work. :( 2021-03-23 14:04:58 -05:00
Shreya Sanghai
dfc86539cc Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
181a28e875 Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00