David Harris
a413b5c6ca
Merge pull request #251 from masonadams25/main
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Removed redundent expression to increase coverage
2023-04-17 12:37:27 -07:00
Ross Thompson
aa2e874d70
Merge pull request #249 from davidharrishmc/dev
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DV Test Plan, fdivsqrt, merged exclusions
2023-04-17 14:32:37 -05:00
Mason Adams
56575cb45e
Removed redundent expression to increase coverage
2023-04-17 14:13:26 -05:00
David Harris
808f60afbb
Started DV Test Plan
2023-04-17 10:18:06 -07:00
David Harris
64fe318cb0
merged coverage exclusions
2023-04-17 10:17:48 -07:00
Ross Thompson
30d017c258
Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.
2023-04-17 12:16:31 -05:00
Ross Thompson
fe692dacce
Finally got the arty a7 to build.
2023-04-17 11:54:22 -05:00
Ross Thompson
4ad33d7acc
OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(
2023-04-17 11:10:19 -05:00
David Harris
bd32b3889f
Merge pull request #248 from dherreravicioso/main
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Added test coverage for reads to HPM counters and coverage exclusions
2023-04-16 18:18:31 -07:00
Ross Thompson
5591b447d6
Fixed more issues with arty a7 constarints.
2023-04-16 13:25:02 -05:00
Diego Herrera Vicioso
16fd17be39
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
2023-04-15 23:13:39 -07:00
Ross Thompson
f4734c0d1b
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
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mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Sydeny
0dc50536ef
trimming comments on fctrl bug fixes
2023-04-15 00:48:32 -07:00
Ross Thompson
30e3d2cdce
Merge pull request #233 from AlecVercruysse/coverage3
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Full I$ coverage
2023-04-14 22:15:11 -05:00
Alec Vercruysse
4d9aa72877
replace instances of code duplication for i$ exclusions w/commands
2023-04-14 17:10:39 -07:00
Ross Thompson
2f8359e6cc
Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
2023-04-14 18:02:16 -05:00
Ross Thompson
13af73e372
Merge pull request #247 from AlecVercruysse/code_quality
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Code Quality
2023-04-14 16:46:39 -05:00
Limnanthes Serafini
49e025bd48
Final small fix
2023-04-14 14:15:52 -07:00
Limnanthes Serafini
ea690a9dfe
Merge branch 'code_quality' of https://github.com/AlecVercruysse/cvw into code_quality
2023-04-14 14:14:40 -07:00
Limnanthes Serafini
2c20079a46
indent fix
2023-04-14 14:14:34 -07:00
Limnanthes Serafini
b0ad690a0a
Merge branch 'openhwgroup:main' into code_quality
2023-04-14 14:13:15 -07:00
David Harris
8e1e981aa2
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-14 12:57:26 -07:00
Ross Thompson
98544d28b0
Merge pull request #245 from Dygore/main
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Added Multiple tests to increase FPU Coverage
2023-04-14 14:51:28 -05:00
Dylan
44574117e8
Merge branch 'openhwgroup:main' into main
2023-04-14 14:41:26 -05:00
Dygore
cac9c2dc37
Added multiple tests to increase FPU coverage
2023-04-14 14:41:05 -05:00
Ross Thompson
d967e05c20
Finally fixed the ddr3 mig script to work correclty.
2023-04-14 11:41:51 -05:00
David Harris
bdc36aafae
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-14 04:16:11 -07:00
David Harris
bc47018fb5
Merge pull request #244 from Dygore/main
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Added tests for full coverage of the FPU result sign module
2023-04-14 04:02:29 -07:00
Dylan
d7936a9214
Merge branch 'openhwgroup:main' into main
2023-04-14 00:36:57 -05:00
Dygore
69b4751162
Added tests for full coverage of the FPU result sign module
2023-04-14 00:36:12 -05:00
Limnanthes Serafini
b3976daccd
More cleanup
2023-04-13 21:34:50 -07:00
Limnanthes Serafini
b80a540c73
More cleanup
2023-04-13 21:02:30 -07:00
Limnanthes Serafini
53847269da
More changes
2023-04-13 21:02:15 -07:00
Limnanthes Serafini
0b6ce1b031
Some cleanup
2023-04-13 21:01:57 -07:00
Limnanthes Serafini
2d9de7b58f
Merge branch 'openhwgroup:main' into code_quality
2023-04-13 19:59:58 -07:00
Limnanthes Serafini
ff72cbc1b2
Finished up testbench reformatting
2023-04-13 19:18:26 -07:00
Limnanthes Serafini
b9c97c6a8c
Further indents
2023-04-13 19:07:43 -07:00
Limnanthes Serafini
44356559bc
testbench code visual improvements
2023-04-13 19:06:09 -07:00
David Harris
48de682ea8
Merged coverage-exclusions
2023-04-13 18:15:23 -07:00
David Harris
17ecb0103e
Merge pull request #243 from Noah-G-L/main
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Pull Request to add tlbKP.S - Fill in cache lines
2023-04-13 18:13:04 -07:00
Noah Limpert
6a23bbea9d
add back K. Box and M. Cook Lsu test
2023-04-13 17:50:18 -07:00
Noah Limpert
3683139637
make pull request more clean
2023-04-13 17:44:09 -07:00
Noah Limpert
b35d5bdbdb
Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways"
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This reverts commit 6acf1dadda
2023-04-13 17:40:39 -07:00
David Harris
21db7a0d68
fdivsqrtfsm coverage attempt to waive a state
2023-04-13 17:40:14 -07:00
Noah Limpert
d012715a60
Revert "Test File for Pull Request, Attempt to fill all four ways"
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This reverts commit e887341c80
2023-04-13 17:28:37 -07:00
David Harris
5066cd99ab
Merge pull request #237 from SydRiley/main
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fctrl coverage at 100% after removing redundancies from conditionals
2023-04-13 17:10:46 -07:00
David Harris
69549a6479
Merge pull request #242 from AlecVercruysse/cachesim
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InvalDelayed warning fix; Miscellaneous typo and indent cleanup
2023-04-13 17:07:47 -07:00
Noah Limpert
034dabee54
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-13 17:00:48 -07:00
Limnanthes Serafini
946ed36131
Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim
2023-04-13 17:00:43 -07:00
Limnanthes Serafini
2e809a4e69
A couple indents->spaces
2023-04-13 17:00:41 -07:00
