Marcus Mellor
fd08ff2e60
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-31 10:29:10 -05:00
Mike Thompson
9abfef7c39
Merge pull request #179 from davidharrishmc/dev
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Fixed broken regression: privileged tests and build root
2023-03-31 10:56:27 -04:00
Marcus Mellor
219176db9b
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-31 09:54:02 -05:00
Marcus Mellor
09b2cd304f
Address comments in openhwgroup/cvw#180
2023-03-31 09:51:33 -05:00
Kevin Kim
2c6359b097
only pass in relevant comparator flag to ALU
2023-03-30 19:15:33 -07:00
Kevin Kim
1e88ec7eac
Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup
2023-03-30 19:04:41 -07:00
Kevin Kim
27a5c9c5d6
Merge branch 'openhwgroup:main' into bitmanip_cleanup
2023-03-30 19:04:36 -07:00
Marcus Mellor
3afd963a9e
Disable coverage for branches tested in fpu.s
2023-03-30 19:44:55 -05:00
David Harris
da53f240d3
Refactored InstrValidNotFlushed into CSR Write signals
2023-03-30 17:06:09 -07:00
David Harris
406bb22b6a
Started factoring out InstrValidNotFlushed from CSRs
2023-03-30 14:56:19 -07:00
David Harris
f34218666a
fctrl updated and buildroot working again
2023-03-30 13:17:15 -07:00
David Harris
9129c3ac22
fctrl continued cleanup
2023-03-30 13:07:39 -07:00
David Harris
01c5d58a64
fctrl continued cleanup
2023-03-30 13:05:56 -07:00
David Harris
b2a102ce79
Started to clean up fctrl
2023-03-30 12:57:14 -07:00
Kip Macsai-Goren
3805cf993a
unnecessary comments cleanup
2023-03-29 19:32:57 -07:00
Kip Macsai-Goren
491ef14b71
Resolved ImperasDV receiving incorrect cause values
2023-03-29 15:04:56 -07:00
David Harris
9d8f9e4428
Reduced number of bits in mcause and medeleg registers
2023-03-29 07:02:09 -07:00
David Harris
59f825a54b
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-29 06:19:10 -07:00
David Harris
f2c24b869d
Simplified fctrl
2023-03-28 21:13:48 -07:00
Alec Vercruysse
46df428e56
add check for legal funct3 for IW instructions
2023-03-28 15:59:48 -07:00
David Harris
92a7e86942
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-28 14:33:18 -07:00
Ross Thompson
d0f8db7939
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-28 16:31:50 -05:00
David Harris
6849eeae0c
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-28 14:27:08 -07:00
Ross Thompson
366a96a0fc
Possible fix for issue 148.
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I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Kevin Kim
582c561cb1
comment formatting
2023-03-28 11:40:19 -07:00
Kevin Kim
926f3d2a5a
Merge branch 'openhwgroup:main' into bitmanip_cleanup
2023-03-28 11:31:18 -07:00
David Harris
64bf9510ad
Added support (untested) for half and quad conversions
2023-03-28 10:53:06 -07:00
David Harris
36a0d35ae5
fixed fp->fp conversions
2023-03-28 10:35:41 -07:00
David Harris
4e50cc3379
support more fp -> fp conversions
2023-03-28 10:28:01 -07:00
David Harris
074fd1d9c3
Fixed fmv decoder
2023-03-28 10:21:33 -07:00
Ross Thompson
e49cf8a028
Merge pull request #169 from davidharrishmc/dev
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PMP Fix to issue 132
2023-03-28 11:49:00 -05:00
David Harris
2e5c50e24a
Fixed RV32 tests after PMP fix
2023-03-28 08:35:23 -07:00
David Harris
e8904411ce
Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
2023-03-28 06:58:17 -07:00
David Harris
2e238c15aa
CSRS privileged coverage test
2023-03-28 04:37:56 -07:00
Ross Thompson
d91188c86e
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-27 11:55:19 -05:00
David Harris
9b7e5cec1f
Removed unnecessary monitor
2023-03-27 09:52:38 -07:00
Ross Thompson
d9691c1542
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-27 10:22:48 -05:00
Lee Moore
4bb7dadc00
Merge branch 'openhwgroup:main' into add-linux
2023-03-27 09:44:13 +01:00
Kevin Kim
5d3260de63
removed unnecessary signal indices
2023-03-26 20:06:55 -07:00
Kevin Kim
f6ce03730a
removed unneccesary input signal from zbb
2023-03-26 19:39:49 -07:00
Ross Thompson
ca4b058373
Modified plic and uart to remove async reset. This removes vivado critical warning.
2023-03-24 20:37:48 -05:00
Ross Thompson
0afba56927
Updated GPIO signal names to reflect book.
2023-03-24 18:55:43 -05:00
Ross Thompson
af8f1fd036
Renamed controllerinputstage to controllerinput to match book.
2023-03-24 17:57:02 -05:00
David Harris
0b0d954e7f
Merged ross's spacing fixes
2023-03-24 15:47:26 -07:00
David Harris
092d34373f
Merge pull request #159 from ross144/main
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Renamed signal to match book
2023-03-24 15:34:59 -07:00
Ross Thompson
46b1bca4fc
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
Ross Thompson
b5a58502d0
Replaced tabs -> spaces cache.
2023-03-24 15:15:38 -05:00
Ross Thompson
b518177a45
Updated EBU to replace tabs with spaces.
2023-03-24 15:01:38 -05:00
Kevin Kim
b70ab0fa5a
Zero/Sign extend mux in Shifter, Zero extend mux in Bitmanip alu
2023-03-24 11:52:51 -07:00
David Harris
4b9b20bce0
Shifter capitalization
2023-03-24 09:01:07 -07:00
