523 Commits

Author	SHA1	Message	Date
Jordan Carlin	e13880accf	Use cp -r for sail	2024-09-30 15:58:31 -07:00
Jordan Carlin	f63b6a8495	Don't install z3 for sail	2024-09-30 15:58:28 -07:00
Jordan Carlin	2c63b8daf3	Remove sail dependencies from package install	2024-09-30 15:58:20 -07:00
Jordan Carlin	8f49c527d9	No more opam	2024-09-30 15:58:11 -07:00
Jordan Carlin	6971c3723d	Use sail binary release	2024-09-30 15:58:04 -07:00
David Harris	07410dff5c	Merge pull request #973 from jordancarlin/arch-test-update ... Test and Makefile Updates	2024-09-30 05:27:34 -07:00
Jordan Carlin	8a58f9556e	Merge branch 'main' of https://github.com/openhwgroup/cvw into arch-test-update	2024-09-29 17:16:05 -07:00
Jordan Carlin	5118a1ff9f	Pin GCC to 13.2.0 to avoid GCC 14 issue with Q extension	2024-09-29 17:03:00 -07:00
Jordan Carlin	14d76b9189	Remove old functcov targets in Makefile	2024-09-29 10:37:08 -07:00
Jordan Carlin	ad09edd17d	Remove remaining ieee testcase	2024-09-29 00:37:26 -07:00
David Harris	7f0c2662b3	Merge pull request #966 from ross144/main ... Updates wsim to fail with invalid --lockstep parameters	2024-09-26 08:48:42 -07:00
Rose Thompson	d9719ac9a0	Updated wsim to not run with invalid --lockstep options.	2024-09-26 10:24:06 -05:00
David Harris	4528a5cebc	Issue 963: VCS rv32gc lockstep simulation	2024-09-26 08:08:59 -07:00
Jordan Carlin	ba6481305f	Merge pull request #959 from davidharrishmc/dev ... Improved robustness of reporting errors from regression; add RV32Zca coverage	2024-09-22 20:31:51 -07:00
David Harris	5171ab0a79	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-09-22 20:27:21 -07:00
David Harris	f5e10ffd5b	Merge pull request #960 from jordancarlin/riscv_softfloat ... Generate RISC-V variant floating point testfloat vectors	2024-09-22 20:26:59 -07:00
David Harris	5d1ff604bf	Increased robustness of reporting errors and warnings with any capitalization	2024-09-22 19:24:47 -07:00
Jordan Carlin	9a0ae3a288	Update regression to run riscv floating point variants	2024-09-20 17:20:18 -07:00
David Harris	97f1ba066d	Updated regression --fcov to run the combined ALL files (much fewer jobs, faster)	2024-09-19 07:48:24 -07:00
James Stine	9e88807ad5	fix some missing hard-coded paths #647	2024-09-18 12:47:08 -05:00
David Harris	dc616680ba	removed waiver from regression	2024-09-14 07:21:44 -07:00
David Harris	1233e267f6	Add license header	2024-09-14 06:38:01 -07:00
Jordan Carlin	ae593ed81d	Merge branch 'main' of https://github.com/openhwgroup/cvw into imperas_verbose	2024-09-10 16:10:05 -07:00
David Harris	a2a2091835	Associated coverage fixes	2024-09-09 18:06:08 -07:00
David Harris	96e7759607	Removed obsolete script	2024-09-09 09:10:49 -07:00
David Harris	f36eb6f73d	Added support for RV64GC coverage and fixed regression so that --fcov doesn't send --lockstep flag to wsim, which messed up wsim	2024-09-07 12:05:48 -07:00
David Harris	6e0b0487dd	Recreated coverage changes	2024-09-05 16:32:45 -07:00
Jordan Carlin	9e98c834f1	Add lockstepverbose flag	2024-08-30 12:32:41 -07:00
Jordan Carlin	80750f2308	Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates	2024-08-29 15:55:54 -07:00
Rose Thompson	e07f303353	Have basic rv32gc functional coverage running with open source riscvISACOV.	2024-08-29 15:29:04 -07:00
Rose Thompson	a1c6bc854e	Fixed a subtle questa sim bug with imperasDV. On some linux systems ... vsim will default to 32-bit mode rather than 64-bit, but the ImperasDV libraries are 64-bit. vsim must run in 64-bit mode.	2024-08-29 14:00:52 -07:00
Rose Thompson	6ad2c2e7a6	Merge pull request #935 from davidharrishmc/dev ... Added lockstep support for RV32. Not all wally privileged tests pass…	2024-08-29 10:45:17 -07:00
David Harris	26f3c2a607	Added lockstep support for RV32. Not all wally privileged tests pass yet	2024-08-29 10:44:37 -07:00
Rose Thompson	2dd897e7e1	Merge pull request #932 from davidharrishmc/dev ... Added temporary --fcov2 option to start adopting open-source riscvISACOV	2024-08-27 08:47:59 -07:00
David Harris	9df38e14b2	Added temporary --fcov2 option to start adopting open-source riscvISACOV	2024-08-27 08:40:44 -07:00
Jordan Carlin	0c4993e1db	Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates	2024-08-25 14:57:22 -07:00
Jordan Carlin	99da7e7b21	Merge pull request #931 from davidharrishmc/dev ... Fixed imperas configuration and updated files for new Imperas/Synopsy…	2024-08-25 14:55:42 -07:00
David Harris	30694f4ed0	Fixed imperas configuration and updated files for new Imperas/Synopsys licenses	2024-08-25 14:46:22 -07:00
Jordan Carlin	f0c5d6e4e7	Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates	2024-08-25 12:14:25 -07:00
Rose Thompson	f603d21826	Updated my name in multiple locations.	2024-08-21 10:50:39 -07:00
Jordan Carlin	3edbdf8e86	Fix VCS testbench argument	2024-08-11 17:15:26 -07:00
Jordan Carlin	cfa3422d61	Fix typo in wsim	2024-08-11 14:20:55 -07:00
Jordan Carlin	d3c759518d	Merge branch 'main' of https://github.com/openhwgroup/cvw into script_updates	2024-08-11 13:18:24 -07:00
Jordan Carlin	533277b134	Merge pull request #903 from davidharrishmc/dev ... Updated regression to avoid iter-elf and fix missing --lockstep	2024-08-11 13:17:13 -07:00
Jordan Carlin	ffcf9a3973	Merge pull request #903 from davidharrishmc/dev ... Updated regression to avoid iter-elf and fix missing --lockstep	2024-08-11 13:17:13 -07:00
Jordan Carlin	78bd6822c6	Add --params argument to wsim and use for overriding top-level params	2024-08-11 13:08:16 -07:00
Jordan Carlin	e6ddebde72	Add number of mismatches exit code to cachesim scripts	2024-08-11 11:02:23 -07:00
Jordan Carlin	c19916a1d0	Allow Verilator to pass extra args at compile time (like -G...)	2024-08-10 12:18:54 -07:00
Jordan Carlin	9a70480ef6	Update CacheSim scripts with new wsim and directory structure. Give simulator choice and switch default to verilator.	2024-08-09 21:50:18 -07:00
Jordan Carlin	55bdb918cf	Update gcc activation method for old distros	2024-08-09 17:07:33 -07:00