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https://github.com/openhwgroup/cvw
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fix some missing hard-coded paths #647
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parent
13dc93c579
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@ -13,8 +13,6 @@
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# pip3 install git+https://github.com/riscv/riscv-isac.git
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# Put ~/.local/bin in $PATH to find riscv_isac and riscv_ctg
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RISCVCTG=/home/harris/repos/riscv-ctg
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#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf -o $RISCVCTG/tests/normalizedfadd.cgf -x 32
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#riscv_isac --verbose debug normalize -c $RISCVCTG/sample_cgfs/dataset.cgf -c $RISCVCTG/sample_cgfs/sample_cgfs_fext/RV32H/fadd_b1.s.cgf -o $RISCVCTG/tests/normalizedfadd16_b1.cgf -x 32
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riscv_ctg -cf $RISCVCTG/tests/normalizedfadd16_b1.cgf -d $RISCVCTG/tests --base-isa rv32i --verbose debug
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@ -1,7 +0,0 @@
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FPGA_AXI_SDC_MODULE_VERSION = 1.0
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FPGA_AXI_SDC_SITE = /home/jpease/repos/fpga-axi-sdc
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FPGA_AXI_SDC_SITE_METHOD = local
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FPGA_AXI_SDC_LICENSE = GPLv2
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$(eval $(kernel-module))
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$(eval $(generic-package))
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@ -30,6 +30,10 @@ export SYN_MW=/home/jstine/MW
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export SYN_memory=/home/jstine/WallyMem/rv64gc/
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#export osumemory=/import/yukari1/pdk/TSMC/WallyMem/rv64gc/
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# Environmental variables for FPGA
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export RISCVCTG=/home/harris/repos/riscv-ctg
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# GCC
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if [ -z "$LD_LIBRARY_PATH" ]; then
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export LD_LIBRARY_PATH=$RISCV/riscv64-unknown-elf/lib
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