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https://github.com/openhwgroup/cvw
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Merge pull request #903 from davidharrishmc/dev
Updated regression to avoid iter-elf and fix missing --lockstep
This commit is contained in:
Jordan Carlin
GitHub
commit
ffcf9a3973
5
Makefile
5
Makefile
@ -8,7 +8,7 @@ all:
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make riscof
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make testfloat
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# make verify
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# make coverage
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make coverage
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# make benchmarks
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# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
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@ -35,6 +35,9 @@ coremark:
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embench:
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cd ${WALLY}/benchmarks/embench; make; make run
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coverage:
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make -C tests/coverage
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clean:
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make clean -C sim
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@ -229,6 +229,13 @@ bpredtests = [
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["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"]
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]
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# list of tests not supported by ImperasDV yet that should be waived during lockstep testing
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lockstepwaivers = [
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"WALLY-q-01.S_ref.elf", # Q extension is not supported by ImperasDV
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"WALLY-cbom-01.S_ref.elf", # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV
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"coverage_ieu.elf" # Issue 881: ImperasDV misinterprets 0x6BF05013 as a grevi rather than an illegal instruction
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]
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##################################
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# Data Types & Functions
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##################################
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@ -282,21 +289,35 @@ def addTests(tests, sim):
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grepfile = grepfile)
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configs.append(tc)
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def addLockstepTestsByDir(dir, config, sim):
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sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
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cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
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for file in os.listdir(dir):
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if file.endswith(".elf"):
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fullfile = os.path.join(dir, file)
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sim_log = sim_logdir + config + "_" + file + ".log"
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grepstring = ""
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tc = TestCase(
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name=file,
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variant=config,
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cmd=cmdPrefix + " " + fullfile + " > " + sim_log,
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grepstr="Mismatches : 0",
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grepfile = sim_log)
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configs.append(tc)
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cmdPrefix="wsim --lockstep --sim " + sim + " " + coverStr + " " + config
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if (os.path.isdir(dir)):
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for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)):
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for file in filenames:
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if file.endswith(".elf"):
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fullfile = os.path.join(dirpath, file)
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fields = fullfile.rsplit('/', 3)
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if (fields[2] == "ref"):
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shortelf = fields[1] + "_" + fields[3]
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else:
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shortelf = fields[2] + "_" + fields[3]
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if (shortelf in lockstepwaivers): # skip tests that itch bugs in ImperasDV
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print(f"{bcolors.WARNING}Skipping waived test {shortelf}{bcolors.ENDC}")
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continue
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sim_log = sim_logdir + config + "_" + shortelf + ".log"
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grepstring = ""
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tc = TestCase(
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name=file,
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variant=config,
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cmd=cmdPrefix + " " + fullfile + " > " + sim_log,
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grepstr="Mismatches : 0",
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grepfile = sim_log)
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configs.append(tc)
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else:
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print("Error: Directory not found: " + dir)
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exit(1)
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def search_log_for_text(text, grepfile):
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"""Search through the given log file for text, returning True if it is found or False if it is not"""
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@ -387,14 +408,6 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode
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addTests(tests64gc_fp, coveragesim)
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elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode
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addLockstepTestsByDir(WALLY+"/tests/functcov/rv64/I", "rv64gc", coveragesim)
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#sim_log = WALLY + "/sim/questa/logs/fcov.log"
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#tc = TestCase(
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# name="lockstep_functcov",
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# variant="rv64gc",
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# cmd="iterelf " + WALLY + "/tests/functcov/rv64/I > " + sim_log,
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# grepstr="SUCCESS! All tests ran without failures",
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# grepfile = sim_log)
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#configs.append(tc)
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elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode
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addTests(tests64gc_nofp, coveragesim)
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if (args.fp):
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@ -409,23 +422,8 @@ else:
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# run derivative configurations and lockstep tests in nightly regression
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if (args.nightly):
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sim_log = WALLY + "/sim/questa/logs/lockstep_coverage.log"
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tc = TestCase(
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name="lockstep_coverage",
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variant="rv64gc",
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cmd="iterelf " + WALLY + "/tests/coverage > " + sim_log,
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grepstr="SUCCESS! All tests ran without failures",
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grepfile = sim_log)
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configs.append(tc)
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sim_log = WALLY + "/sim/questa/logs/lockstep_wally-riscv-arch-test.log"
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tc = TestCase(
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name="lockstep_wally-riscv-arch-test",
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variant="rv64gc",
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cmd="iterelf " + WALLY + "/tests/riscof/work/wally-riscv-arch-test/rv64i_m > " + sim_log,
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grepstr="SUCCESS! All tests ran without failures",
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grepfile = sim_log)
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configs.append(tc)
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addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", "questa")
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addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", "questa")
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addTests(derivconfigtests, defaultsim)
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# testfloat tests
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10
bin/wsim
10
bin/wsim
@ -49,7 +49,15 @@ elif (args.elf != ""):
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if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; check if testsuite has a .elf extension and use that instead
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if (os.path.isfile(args.testsuite)):
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ElfFile = "+ElfFile=" + os.path.abspath(args.testsuite)
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if ('/' in args.testsuite):
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# extract the elf name from the path to be the test suite
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fields = args.testsuite.rsplit('/', 3)
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# if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates.
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if (len(fields) > 3):
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if (fields[2] == "ref"):
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args.testsuite = fields[1] + "_" + fields[3]
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else:
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args.testsuite = fields[2] + "_" + fields[3]
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elif ('/' in args.testsuite):
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args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present
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else:
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print("ELF file not found: " + args.testsuite)
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@ -222,7 +222,7 @@ vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${ParamArgs}
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vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} $temp0 $temp1 $temp2 $temp3 -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} ${FCTRACE2COV} ${FCdefineIDV_TRACE2COV} -suppress 3829 ${CoverageVsimArg}
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# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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# power add generates the logging necessary for said generation.
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# power add generates the logging necessary for saif generation.
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# power add -r /dut/core/*
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if { ${GUI} } {
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add log -recursive /*
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@ -151,8 +151,7 @@ module decompress import cvw::*; #(parameter cvw_t P) (
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5'b10000: if (rds1 != 5'b0) begin
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if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli; shamt[5] must be 0 in RV32C
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end else if (immSH != 0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with rd = 0, immm != 0 is a HINT, treated as nop
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5'b10001: if (P.ZCD_SUPPORTED)
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if (rds1 != 5'b0) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
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5'b10001: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
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5'b10010: if (rds1 != 5'b0) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
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5'b10011: if (P.XLEN == 32) begin
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if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
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