bbracker
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07ff0940a3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-03 00:30:49 -04:00 |
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bbracker
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a202c705cd
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checkpoint generator bugfixes
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2021-10-03 00:30:04 -04:00 |
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David Harris
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dcbbee6623
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More divider cleanup
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2021-10-03 00:20:35 -04:00 |
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David Harris
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6aa2521959
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Eliminated extra inversion for subtraction in divider
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2021-10-03 00:10:12 -04:00 |
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David Harris
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371f9d9a4a
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Added more pipeline stage suffixes to divider
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2021-10-03 00:06:57 -04:00 |
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David Harris
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24bb3f4baf
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Added more pipeline stage suffixes to divider
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2021-10-02 22:54:01 -04:00 |
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David Harris
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3441991d93
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Divider mostly cleaned up
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2021-10-02 21:10:35 -04:00 |
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David Harris
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67690c2ed7
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Partial divider cleanup 3
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2021-10-02 21:00:13 -04:00 |
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David Harris
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775520c05a
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Partial divider cleanup 2
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2021-10-02 20:57:54 -04:00 |
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David Harris
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fe69513bb7
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Partial divider cleanup
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2021-10-02 20:55:37 -04:00 |
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David Harris
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a86ce5cd37
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Divider code cleanup
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2021-10-02 10:41:09 -04:00 |
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David Harris
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d532bde931
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Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division
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2021-10-02 10:36:51 -04:00 |
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David Harris
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d4437b842a
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Divider code cleanup
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2021-10-02 10:13:49 -04:00 |
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David Harris
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0e0e204d3d
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Moved negating divider otuput to M stage
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2021-10-02 10:03:02 -04:00 |
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David Harris
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735132191c
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Moved muldiv result selection to M stage for performance
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2021-10-02 09:38:02 -04:00 |
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David Harris
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73d852b1ef
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Divide performs 2 steps per cycle
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2021-10-02 09:19:25 -04:00 |
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David Harris
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35e5a5cef3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-09-30 23:15:34 -04:00 |
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bbracker
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5022647041
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Revert "first attempt at verilog side of checkpoint functionality"
This reverts commit f6ef8e5656.
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2021-09-30 20:45:26 -04:00 |
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David Harris
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a39e14663d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-09-30 20:07:43 -04:00 |
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David Harris
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a8573a27d4
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Integer Divide/Rem passing all regression.
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2021-09-30 20:07:22 -04:00 |
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David Harris
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953c8931ed
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RV32 div/rem working signed and unsigned
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2021-09-30 15:24:43 -04:00 |
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Ross Thompson
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ec4a07de64
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Movied tristate to test bench level.
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2021-09-30 11:27:42 -05:00 |
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Ross Thompson
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db18aac9af
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Partially sd card read on fpga.
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2021-09-30 11:23:09 -05:00 |
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David Harris
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e1ad732178
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SRT Division unsigned passing Imperas tests
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2021-09-30 12:17:24 -04:00 |
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bbracker
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f6ef8e5656
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first attempt at verilog side of checkpoint functionality
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2021-09-28 23:17:58 -04:00 |
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bbracker
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a47448c4d0
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first attemtpt at checkpoint infrastructure
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2021-09-28 22:33:47 -04:00 |
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Ross Thompson
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99070127d8
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Added debugging directives to system verilog.
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2021-09-27 13:57:46 -05:00 |
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bbracker
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2ffdbdf6d2
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condense testbench code; debug_level of 0 means don't check at all
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2021-09-27 03:03:11 -04:00 |
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Ross Thompson
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f2c1ca4bd5
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added support to due partial fpga simulation.
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2021-09-26 15:00:00 -05:00 |
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Ross Thompson
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6ac96db20b
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Merge branch 'main' into fpga
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2021-09-26 13:22:53 -05:00 |
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Ross Thompson
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6dc25e07c2
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Updated the fpga bios code to emulate the same behavior as qemu's bootloader and it also copies
the flash card to dram.
Fixed latch issue in the sd card reader.
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2021-09-26 13:22:23 -05:00 |
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Ross Thompson
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55f3c15302
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Merge branch 'sdc' into fpga
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2021-09-25 19:33:07 -05:00 |
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Ross Thompson
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8e29d4472e
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GPIO marker to indicate the sdc to dram transfer complete.
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2021-09-25 19:29:15 -05:00 |
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Ross Thompson
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5bdd6a9d0c
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Almost done writting driver for flash card reader.
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2021-09-25 19:05:07 -05:00 |
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Ross Thompson
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3a15cc7872
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We now have a rough sdc read routine.
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2021-09-25 17:51:38 -05:00 |
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Ross Thompson
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43d386f9f3
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Updated ignore file.
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2021-09-24 18:48:45 -05:00 |
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Ross Thompson
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dd9fe60b28
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Write of the SDC address register is correct. The command register is not yet working.
The root problem is the command register needs to be reset at the end of the SDC transaction.
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2021-09-24 18:48:11 -05:00 |
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Ross Thompson
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5663522a3f
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Now have software interacting with the initialization and settting the address register.
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2021-09-24 18:30:26 -05:00 |
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Ross Thompson
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232d4a554f
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Have program which checks for sdc init and issues read, but read done is
not correctly being read back by the software. The error is in how the
sdc indicates busy.
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2021-09-24 15:53:38 -05:00 |
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Kip Macsai-Goren
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077f125c13
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updated pmp outputs with new exectuaion tests
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2021-09-24 16:30:16 -04:00 |
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Kip Macsai-Goren
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cd5b4034e5
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updated execute tests, light cleanup, privilege mode changes still need fix.
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2021-09-24 16:29:56 -04:00 |
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Kip Macsai-Goren
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603667e1e6
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updated test library to include: simpler execution tests, widths for each read/write, outputs for pmpaddr writes.
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2021-09-24 16:28:53 -04:00 |
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Kip Macsai-Goren
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bb0bc816c5
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completed and cleaned up pmp tests, including execute tests
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2021-09-24 16:18:44 -04:00 |
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Ross Thompson
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71e20c7f61
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Fixed lint errors in the SDC.
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2021-09-24 12:38:48 -05:00 |
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Ross Thompson
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0f87f68b9d
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Added either the sdModel or constant driver for the SDC ports in all test benches.
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2021-09-24 12:31:51 -05:00 |
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Ross Thompson
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af28cfb70c
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Added SDC defines to each config mode.
Added sd_top which is the sd card reader.
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2021-09-24 12:24:30 -05:00 |
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Ross Thompson
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0a33f5fa46
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setup so the sdc does not need to load a model in the imperas test bench.
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2021-09-24 11:30:52 -05:00 |
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Ross Thompson
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78028947bf
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Updated Imperas test bench to work with the SDC reader.
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2021-09-24 11:22:54 -05:00 |
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Ross Thompson
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4256ef82b1
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SDC to ABHLite interface partially done.
Added SDC to adrdec and uncore.
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2021-09-24 10:45:09 -05:00 |
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Ross Thompson
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a182263b1c
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Added clock gater and divider to generate the SDCCLK.
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2021-09-23 17:58:50 -05:00 |
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