David Harris
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1c1acc467e
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Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0
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2024-10-26 02:01:09 -07:00 |
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naichewa
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3b7661dfd5
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SckDiv Zero bug fixes
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2024-09-03 14:58:46 -07:00 |
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Jacob Pease
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d8b75440b6
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With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
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2024-08-20 16:24:37 -05:00 |
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David Harris
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b3661a0af4
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Removed unused WALLY-lrsc reference outputs that were incorrect and are not used because Sail is the reference instead
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2024-03-24 12:31:49 -07:00 |
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David Harris
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824bc0dab7
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Fixed expected value on WALLY-satp-invalid
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2024-02-16 11:12:57 -08:00 |
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David Harris
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caedab679a
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Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x
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2024-01-07 07:14:12 -08:00 |
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Rose Thompson
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418ae0decc
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Fixed some regression tests with David's help.
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2023-12-19 14:18:21 -06:00 |
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David Harris
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6c017141c5
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Renamed HADE to ADUE for Svadu
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2023-12-13 11:49:04 -08:00 |
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naichewa
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a5837eb62c
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fifo fixes and edge case testing
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2023-11-07 17:59:46 -08:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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David Harris
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f6a7f707bd
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Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
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2023-10-30 09:56:17 -07:00 |
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naichewa
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0ff9ce527d
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Merge branch 'main' into spi
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2023-10-16 22:59:50 -07:00 |
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David Harris
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ac4216b43d
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Incorporated new AMO tests from riscv-arch-test
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2023-10-16 10:25:45 -07:00 |
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David Harris
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6245748ed7
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Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
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2023-10-15 15:31:03 -07:00 |
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David Harris
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b4891d88db
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Added WALLY minfo test for rv32
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2023-10-15 06:48:22 -07:00 |
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naichewa
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aa5abfc8e8
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always working after reg bit swizzle changes
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2023-10-13 14:22:32 -07:00 |
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naichewa
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d5d4f9d044
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transferred spi changes in ECA-authorized commit
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2023-10-12 13:36:57 -07:00 |
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David Harris
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d526d28804
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Added MENVCFG.HADE bit and updated SVADU to depend on this bit
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2023-10-04 09:34:28 -07:00 |
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David Harris
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8d3ff59673
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Completed basic tests of svnapot and svpbmt
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2023-08-28 06:57:35 -07:00 |
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Ross Thompson
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cd3349bd26
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Added rv32 cboz test.
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2023-08-24 17:02:53 -05:00 |
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Ross Thompson
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7d51690b7c
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Oups forgot to include the 32-bit cbom test in previous commit.
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2023-08-24 09:04:41 -05:00 |
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David Harris
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c137a1c8cf
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Fixed timer interrupt testing
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2023-06-09 17:20:41 -07:00 |
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David Harris
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b70b0c7c5e
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Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare
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2023-06-09 14:40:01 -07:00 |
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Kip Macsai-Goren
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34200e8c76
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restored original virt mem tests when svadu is not supported
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2023-04-11 18:47:08 -07:00 |
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Kip Macsai-Goren
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c4766c8a02
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renamed virt mem tests to include svadu
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2023-04-11 18:46:37 -07:00 |
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Kip Macsai-Goren
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b2d6084eea
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removed unnecessary 'deadbeef's at the end of reference outputs
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2023-04-11 18:32:04 -07:00 |
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Kip Macsai-Goren
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a82c0a7780
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Modified virt mem tests to do correct r/w when svadu is enabled
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2023-04-11 18:08:30 -07:00 |
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Kip Macsai-Goren
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e0b938b409
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Removed Trap outputs from writes covered by SVADU
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2023-04-11 17:41:57 -07:00 |
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Kip Macsai-Goren
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a7c9d3d37b
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ported medelg fixes to 32 bit tests. Requires a make allclean
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2023-03-29 16:31:28 -07:00 |
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David Harris
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2e5c50e24a
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Fixed RV32 tests after PMP fix
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2023-03-28 08:35:23 -07:00 |
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Kip Macsai-Goren
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758da62a9f
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ported fixes to 32 bit tests
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2023-03-24 11:22:39 -07:00 |
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Kip Macsai-Goren
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964084f0b3
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added fs=00 to status fp enabled test
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2022-12-22 15:15:53 -08:00 |
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Kip Macsai-Goren
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d25d699800
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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Kip Macsai-Goren
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4c81b6fa5f
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added corrrect scr read out of uart to periph test
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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51e78d9e48
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added copies of 64 bit tests to 32 bit periph and priv tests
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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540d6c2f41
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added -01 to all WALLY tests
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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6e45698b86
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Added test for UART FIFO timeout. Does not pass regression
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2022-10-25 05:35:56 +00:00 |
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Kip Macsai-Goren
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e603973dff
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added xlen and endianness test edits. xlen passes but endinanness still won't make
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2022-09-26 05:03:19 +00:00 |
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Kip Macsai-Goren
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0cc7f5719c
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ported endianness tests to 32 bits (not tested in regression yet)
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2022-09-18 00:10:29 +00:00 |
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David Harris
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898dbc8e74
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Completed PLIC-S tests. Regression working. This completes peripheral tests.
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2022-08-03 09:33:56 -07:00 |
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David Harris
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cab0349701
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Started plic-s tests
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2022-08-03 03:48:08 +00:00 |
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David Harris
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93d7d7179e
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Added parity and stop bit tests to UART
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2022-07-28 04:35:51 +00:00 |
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David Harris
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429bdae1c4
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Fixed UART reference output
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2022-07-27 22:16:38 +00:00 |
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David Harris
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b08c87cb47
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Finished UART test
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2022-07-27 04:06:59 +00:00 |
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slmnemo
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7348af7fd5
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Updated reference file for UART test
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2022-07-26 09:39:31 -07:00 |
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slmnemo
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bfced6bfe8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 17:13:38 -07:00 |
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slmnemo
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ca4511b6dc
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Fixed UART FIFO bugs and added FIFO tests
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2022-07-22 17:13:19 -07:00 |
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Daniel Torres
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4da96c5791
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fixed 32priv tests, now passing
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2022-07-22 15:35:20 -07:00 |
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Daniel Torres
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24828db612
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changes to test.vh for compatability
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2022-07-22 15:00:48 -07:00 |
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slmnemo
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141f2a40e4
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UART updates and PMA fix
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2022-07-22 14:49:03 -07:00 |
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