Ross Thompson
4ddbbd6948
Merge pull request #314 from davidharrishmc/dev
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Make and FP script improvements
2023-06-06 12:38:26 -04:00
James Stine
ac3253203d
Update fcvt tests for l.s/lu.s and s.l/s.lu that were missing
2023-06-05 11:03:59 -05:00
David Harris
1831dfccc2
Fixed paths in creating division test vectors
2023-05-31 06:30:41 -07:00
David Harris
b5f70013b1
Clean up combined int/fp vector creation
2023-05-30 14:01:12 -07:00
David Harris
b4c9998b26
Increased timeout for riscof because it is so slow
2023-05-23 15:37:09 -07:00
David Harris
19096a812a
Added Zifencei ISA to tests where necessary to support new compiler
2023-05-16 11:18:27 -07:00
David Harris
0a7a159d69
Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile
2023-05-14 06:58:29 -07:00
David Harris
0cc8f9fd15
Fixed riscof scripts that were removing zicsr from compiler misa
2023-05-14 04:19:08 -07:00
David Harris
67a089104c
Defined empty RVMODEL interrupt macros to make riscof warnings go away
2023-05-14 03:36:28 -07:00
Kevin Thomas
0c9b7dcce7
Comment tlbGBL more discriptively
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Reduce redundant instructions
2023-05-04 19:13:47 -05:00
David Harris
ec3518673e
Merge branch 'main' into main
2023-04-28 07:51:32 -07:00
Liam Chalk
028d19bbfa
Merge branch 'main' into main
2023-04-27 21:49:01 -07:00
Kevin Wan
39c9cd5ee9
added tests for pmppriority module
2023-04-27 16:12:43 -07:00
David Harris
15fb5fa2ac
Update tlbASID.S
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fixed comment about restoring ASID to 0
2023-04-27 14:32:57 -07:00
Noah Limpert
4ec31de316
complete camline coverage on IFU and LSU
2023-04-27 14:26:10 -07:00
Liam
4d8eafd27d
Pmpadrdecs test cases changing AdrMode to 2 or 3
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Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
2023-04-27 12:23:35 -07:00
Alexa Wright
09095422d0
Merge branch 'openhwgroup:main' into main
2023-04-26 16:26:30 -07:00
Alexa Wright
59d913949f
Excluded and added coverage for WFI test case.
2023-04-25 17:06:57 -07:00
Liam
7bf2ee5418
pmpaddr0 and pmpaddr2 test cases
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Writing 0x00170000 and 0x17000000 to pmpaddr0 and pmpaddr2.
Increased IFU coverage from 83.53% to 83.68% and LSU coverage from 93.29% to 93.45%.
2023-04-25 15:37:04 -07:00
David Harris
086556310c
Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
2023-04-22 12:22:45 -07:00
Liam
c2f441724b
pmpcfg test cases
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Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
2023-04-21 20:43:37 -07:00
Noah Limpert
a0e71c26cb
Add in a test that makes match 3 = 0 for all tlb lines
2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126
Commiting changes to add coverage to ASID, Global, Megapage size checks.
2023-04-20 14:38:13 -07:00
Liam
4f57dca0dc
Add pmpcfg test cases increasing IFU coverage
2023-04-19 11:58:22 -07:00
David Harris
4cbffd7972
Merge branch 'main' into coverage4
2023-04-19 06:16:07 -07:00
David Harris
b63dff098a
Merge branch 'main' into main
2023-04-19 04:50:12 -07:00
Alec Vercruysse
b3a3af8ed3
add D$ test case to trigger a FlushStage while SetDirtyWay=1
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This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44
Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
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This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
2023-04-19 01:34:01 -07:00
Liam
d74768ce04
Add test cases for pmpcfg.S
2023-04-18 23:06:52 -07:00
Kevin Wan
b5a3ff2d2d
a
2023-04-18 22:09:50 -07:00
Kevin Wan
c91784bd5a
Merge branch 'main' of https://github.com/koooo142857/cvw into main
2023-04-18 21:55:06 -07:00
koooo142857
c9018b8204
Merge branch 'openhwgroup:main' into main
2023-04-18 21:53:46 -07:00
Kevin Wan
771124e265
Completely covers all PMPCFG_ARRAY_REGW cases
2023-04-18 21:50:48 -07:00
Kevin Wan
1bdae2285d
PMPCFG_ARRAY_REGW cases
2023-04-18 18:43:50 -07:00
Miles Cook
5e45fef838
Increase of TLB coverage in IFU
2023-04-17 18:35:03 -07:00
Diego Herrera Vicioso
16fd17be39
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
2023-04-15 23:13:39 -07:00
Dygore
cac9c2dc37
Added multiple tests to increase FPU coverage
2023-04-14 14:41:05 -05:00
Dylan
d7936a9214
Merge branch 'openhwgroup:main' into main
2023-04-14 00:36:57 -05:00
Dygore
69b4751162
Added tests for full coverage of the FPU result sign module
2023-04-14 00:36:12 -05:00
Noah Limpert
6a23bbea9d
add back K. Box and M. Cook Lsu test
2023-04-13 17:50:18 -07:00
Noah Limpert
3683139637
make pull request more clean
2023-04-13 17:44:09 -07:00
Noah Limpert
b35d5bdbdb
Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways"
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This reverts commit 6acf1dadda
2023-04-13 17:40:39 -07:00
Noah Limpert
d012715a60
Revert "Test File for Pull Request, Attempt to fill all four ways"
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This reverts commit e887341c80
2023-04-13 17:28:37 -07:00
Noah Limpert
034dabee54
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-13 17:00:48 -07:00
Noah Limpert
a0a9d35d19
update tests.vh, add tlbKP to load all lines of tlb
2023-04-13 15:13:55 -07:00
Dygore
4854e09124
Added a test for denormalized FP numbers
2023-04-13 16:39:27 -05:00
Noah Limpert
276ce87582
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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pull in changes to trap handler so that permissions should change correctly
2023-04-13 12:34:27 -07:00
Alexa Wright
23d0d45bf6
Fixed exception handling to handle ecalls properly
2023-04-13 09:23:32 -07:00
Kip Macsai-Goren
34200e8c76
restored original virt mem tests when svadu is not supported
2023-04-11 18:47:08 -07:00
Kip Macsai-Goren
c4766c8a02
renamed virt mem tests to include svadu
2023-04-11 18:46:37 -07:00
