Rose Thompson
dc09e1c0c5
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
Rose Thompson
73261e7f89
More cleanup. Close to the simpliest it can be.
2024-05-24 16:34:33 -05:00
Rose Thompson
bd2ec879d2
Removed unused axi signals from packetizer.
2024-05-24 16:31:27 -05:00
Rose Thompson
263be86119
Packetizer cleanup.
2024-05-24 16:27:09 -05:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Rose Thompson
d341974c5b
Have rvvi to ethernet working.
...
Now it is time to move the hardware to the FPGA.
Ideally I don't want Wally to actually have any of this code since it's entirely
debug code so it will move to the fpga/src directory.
Then we'll need to add additional logic to the mmcm to generate the correct clocks.
Finally we'll update the I/O to add ethernet.
2024-05-24 15:52:13 -05:00
Rose Thompson
bf9f45d319
We have a simulation of the ethernet transmission working.
...
This commit does not include the source files for the ethernet as it does not belong to cvw.
I'll want to fork that repo and make it a submodule as I need to change the source a bit.
2024-05-24 11:25:42 -05:00
Rose Thompson
e5b8fd35b0
Successfully added RVVIStall for back pressure to slow down the pipeline if the ethernet or host computer running imperasDV can't keep up.
2024-05-22 09:56:12 -05:00
Rose Thompson
b116c0c902
Lots of progress on the rvvisynth to ethernet packetizer.
...
Almost producing axi4 commands.
2024-05-21 18:23:42 -05:00
Rose Thompson
d1141237ee
Removed prefix from rvvi hierarchy so it works without testbench.
2024-05-21 16:20:53 -05:00
Rose Thompson
8fd278b322
Fixed some references to rvvi.
2024-05-21 16:15:05 -05:00
Rose Thompson
ea5d780adf
Closer to synthesized rvvi
2024-05-21 12:42:43 -05:00
Rose Thompson
b127c19242
Merge branch 'main' into rvvi
2024-05-20 16:31:06 -05:00
Rose Thompson
d6b4a1fc83
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-20 16:23:57 -05:00
Rose Thompson
d025bd0aff
More improvements to the readme.
2024-05-20 16:23:25 -05:00
Rose Thompson
33eb5980e7
More readme formating.
2024-05-20 15:57:45 -05:00
Rose Thompson
7cc1fcbd49
More formating.
2024-05-20 15:52:36 -05:00
Rose Thompson
55008e98c9
Formated readme.
2024-05-20 15:50:17 -05:00
Rose Thompson
ad568e9d25
Updated readme.
2024-05-20 15:46:26 -05:00
David Harris
c32090067f
Merge pull request #806 from ross144/main
...
Merge testbench-imperas.sv into testbench.sv
2024-05-18 06:28:29 +01:00
Rose Thompson
6e3ccbb9c1
Almost have it working for both buildroot and single elfs.
2024-05-17 17:34:29 -05:00
Rose Thompson
224b2e4dc4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-17 17:10:28 -05:00
Rose Thompson
e008999030
wsim now supports lockstep and single elf
...
example
wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --elf --lockstep
2024-05-17 17:10:15 -05:00
Rose Thompson
0ed75a3ff5
Reverted testbench-imperas.sv incase someone wants this.
2024-05-17 16:48:29 -05:00
Rose Thompson
038aae388b
Yay. Finally found the issue with the integrated testbench.sv and imperasDV.
...
The function which loads the elf file rvviRefInit must be called during an initial block
using a valid file name. Because of how the testbench was organized the elffile was not defined
until several cycles later so the call to rvviRefInit did not have a valid elf. Waiting several
cycles does not work. rvviRefInit requires being called in an initial block so it is not possible
to run back to back imperasDV simulations in the same run.
2024-05-17 16:45:01 -05:00
Rose Thompson
e6902eb4d2
Ok. How does it still work? testbench-imperas.sv the same as testbench.sv now.
2024-05-17 16:08:14 -05:00
Rose Thompson
d9807bb909
This is crazy. I'm merging testbench.sv into testbench-imperas.sv to find the point when it stops working. But each logical point where it would stop working it keeps working. For example moving readmemh from initial to always block.
2024-05-17 14:45:37 -05:00
Rose Thompson
a885240fbd
temporary commit to help debug merging testbench.sv with testbench-imperas.sv
2024-05-17 12:36:00 -05:00
Rose Thompson
bd8450734b
Fixed more bugs with wally.do.
2024-05-17 10:39:00 -05:00
Rose Thompson
62eaca0e6e
Almost working ImperasDV with testbench.sv and wally.do. For some reason IDV is saying the instructions are mismatching.
2024-05-16 17:01:25 -05:00
Rose Thompson
9a42aab971
Merge pull request #804 from jordancarlin/dev
...
Eliminate more logical operators and replace with bitwise operators
2024-05-16 15:45:18 -05:00
Rose Thompson
8391b8b821
Progress towards unified regression.
2024-05-16 15:29:12 -05:00
Rose Thompson
3fdfa0f705
wsim now simulates a single elffile.
2024-05-16 15:14:49 -05:00
Rose Thompson
08601d7270
Added functionallity to testbench.sv for single elf files.
2024-05-16 13:59:15 -05:00
David Harris
5e02ce6697
Merge pull request #805 from jordancarlin/Zcb_fix
...
Certain Zcb instructions are dependent on other extensions, not the entire extension
2024-05-15 19:28:14 -07:00
Jordan Carlin
1d8ffee20c
Certain Zcb instructions are dependent on other extensions, not the entire extension
2024-05-15 19:16:43 -07:00
Jordan Carlin
ef778da98d
Eliminate more logical operators and replace with bitwise
2024-05-15 10:50:23 -07:00
Rose Thompson
4c7cec77fe
Merge pull request #803 from jordancarlin/dev
...
Switch riscvassertions to use bitwise operators instead of logical operators per Wally style guide
2024-05-15 11:37:09 -05:00
Jordan Carlin
3df5a5abdd
Remove additional bitwise operator
2024-05-15 09:29:54 -07:00
Jordan Carlin
4ffce9a752
Switch riscvassertions to use bitwise operators instead of logical operators per Wally style guide
2024-05-15 09:23:24 -07:00
Rose Thompson
e295454948
Merge pull request #798 from jordancarlin/newConfig
...
Update config to derive MISA from macros and update MISA bits based on the spec
2024-05-15 10:28:44 -05:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
David Harris
fccf40da1f
Merge pull request #802 from ross144/main
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Merge wally-linux-imperas.do with wally.do
2024-05-14 18:46:07 -07:00
Jordan Carlin
bf397f791f
Change all SUPPORTED type localparamters to one bit logic. Update configs for consistency.
2024-05-14 16:24:26 -07:00
Jordan Carlin
1065b8977a
Fix Q_SUPPORTED on derived configs
2024-05-14 11:49:54 -07:00
Rose Thompson
46e6459965
Updated script to run linux with imperasDV.
2024-05-14 13:46:27 -05:00
Rose Thompson
a0686c95a0
Merge branch 'openhwgroup:main' into main
2024-05-14 13:42:16 -05:00
Rose Thompson
970af9551c
Fixed bug with gui mode testbench_fp
...
removed old wally-linux-imperas.do
2024-05-14 13:41:20 -05:00
Rose Thompson
4cc8859612
Updated wsim to use --coverage rather than -coverage.
2024-05-14 13:31:34 -05:00
Rose Thompson
1874226b60
Merge pull request #799 from davidharrishmc/dev
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Parameterized FMA, fpcalc supports quad
2024-05-14 13:17:32 -05:00
