mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'openhwgroup:main' into main
This commit is contained in:
Rose Thompson
GitHub
commit
a0686c95a0
@ -115,6 +115,9 @@ localparam CVTLEN = (ZFA_SUPPORTED & D_SUPPORTED) ? `max(BASECVTLEN, 32'd84) : B
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localparam LLEN = `max($unsigned(FLEN), $unsigned(XLEN));
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localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
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// size of FMA output
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localparam FMALEN = 3*NF + 6;
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// NORMSHIFTSIZE is the bits out of the normalization shifter
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// RV32F: max(32+23+1, 2(23)+4, 3(23)+6) = 3*23+6 = 75
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// RV64F: max(64+23+1, 64 + 23 + 2, 3*23+6) = 89
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@ -125,12 +128,10 @@ localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
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// because NORMSHIFTSZ becomes limited by convert rather than divider
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// The two extra bits are necessary because shiftcorrection dropped them for fcvt.
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// May be possible to remove these two bits by modifying shiftcorrection
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localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1+2), (DIVb + 1 + NF + 1)), (3*NF+8));
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//localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (3*NF+8));
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//localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1+2), (DIVb + 1 + NF + 1)), (FMALEN + 2));
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localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2));
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localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); // log_2(NORMSHIFTSZ)
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localparam CORRSHIFTSZ = NORMSHIFTSZ-2; // Drop leading 2 integer bits
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// Disable spurious Verilator warnings
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@ -193,9 +193,9 @@ localparam cvw_t P = '{
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CVTLEN : CVTLEN,
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LLEN : LLEN,
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LOGCVTLEN : LOGCVTLEN,
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FMALEN : FMALEN,
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NORMSHIFTSZ : NORMSHIFTSZ,
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LOGNORMSHIFTSZ : LOGNORMSHIFTSZ,
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CORRSHIFTSZ : CORRSHIFTSZ,
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LOGR : LOGR,
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RK : RK,
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FPDUR : FPDUR,
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@ -2,14 +2,12 @@
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CC = gcc
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CFLAGS = -O3 -Wno-format-overflow
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LIBS = -lm
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LFLAGS = -L.
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# Link against the riscv-isa-sim version of SoftFloat rather than
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# the regular version to get RISC-V NaN behavior
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IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
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LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
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LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -lm -lquadmath
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#IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
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#LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
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#LIBS = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
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SRCS = $(wildcard *.c)
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PROGS = $(patsubst %.c,%,$(SRCS))
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@ -17,7 +15,7 @@ PROGS = $(patsubst %.c,%,$(SRCS))
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all: $(PROGS)
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%: %.c
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$(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
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$(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
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clean:
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rm -f $(PROGS)
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@ -7,6 +7,8 @@
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <inttypes.h>
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#include <quadmath.h> // GCC Quad-Math Library
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#include "softfloat.h"
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#include "softfloat_types.h"
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@ -26,6 +28,12 @@ typedef union dp {
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double d;
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} dp;
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typedef union qp {
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uint64_t v64[2];
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__uint128_t v;
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__float128 q;
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} qp;
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int opSize = 0;
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@ -140,6 +148,45 @@ void printF64(char *msg, float64_t f) {
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// msg, conv.v, conv.d, sci, exp, fract);
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}
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void printF128 (char *msg, float128_t q) {
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qp conv;
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//__int128_t v128;
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int i, j;
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char buf[64];
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//v128 = q.v[1];
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//v128 = v128 << 64 | q.v[0]; // use union to convert between hexadecimal and floating-point views
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//conv.v = v128;
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conv.v64[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
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conv.v64[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views
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printf("%s: ", msg); // print out nicely
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// Some compilers can understand %Q for printf on quad precision instead of the
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// API call of quadmath_snprintf
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// printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
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quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
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//printf("0x%032" PRIx12 " = %s\n", q.v, buf);
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printf("0x%016" PRIx64 "_%016" PRIx64 " = %s\n", q.v[1], q.v[0], buf);
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}
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void printF128val(float128_t q) {
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qp conv;
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//__int128_t v128;
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int i, j;
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char buf[64];
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//v128 = q.v[1];
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//v128 = v128 << 64 | q.v[0]; // use union to convert between hexadecimal and floating-point views
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//conv.v = v128;
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conv.v64[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
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conv.v64[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views
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// Some compilers can understand %Q for printf on quad precision instead of the
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// API call of quadmath_snprintf
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// printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
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//quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
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printf("%016" PRIx64 "%016" PRIx64 "\n", q.v[1], q.v[0]);
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}
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void printFlags(void) {
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int NX = softfloat_exceptionFlags % 2;
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int UF = (softfloat_exceptionFlags >> 1) % 2;
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@ -160,14 +207,32 @@ void softfloatInit(void) {
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softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
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}
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uint64_t parseNum(char *num) {
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uint64_t result;
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__uint128_t strtoul128(char *num, int base) {
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__uint128_t result = 0;
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int i;
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for (i=0; i<strlen(num); i++) {
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result = result * base;
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if (num[i] >= '0' && num[i] <= '9') result += num[i] - '0';
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else if (num[i] >= 'a' && num[i] <= 'f') result += num[i] - 'a' + 10;
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else if (num[i] >= 'A' && num[i] <= 'F') result += num[i] - 'A' + 10;
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else {
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printf("Error: bad character %c in number %s\n", num[i], num);
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exit(1);
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}
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}
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return result;
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}
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__uint128_t parseNum(char *num) {
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// uint64_t result;
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__uint128_t result;
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int size; // size of operands in bytes (2= half, 4=single, 8 = double)
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if (strlen(num) < 8) size = 2;
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else if (strlen(num) < 16) size = 4;
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else if (strlen(num) < 19) size = 8;
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else if (strlen(num) < 32) size = 8;
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else if (strlen(num) < 35) size = 16; // *** will need to increase
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else {
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printf("Error: only half, single, and double precision supported");
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printf("Error: only half, single, double, or quad precision supported");
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exit(1);
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}
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if (opSize != 0) {
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@ -179,7 +244,7 @@ uint64_t parseNum(char *num) {
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opSize = size;
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//printf ("Operand size is %d\n", opSize);
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}
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result = (uint64_t)strtoul(num, NULL, 16);
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result = (__uint128_t)strtoul128(num, 16);
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//printf("Parsed %s as 0x%lx\n", num, result);
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return result;
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}
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@ -206,7 +271,8 @@ char parseRound(char *rnd) {
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int main(int argc, char *argv[])
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{
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uint64_t xn, yn, zn;
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//uint64_t xn, yn, zn;
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__uint128_t xn, yn, zn;
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char op1, op2;
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char cmd[200];
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@ -217,6 +283,7 @@ int main(int argc, char *argv[])
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exit(1);
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} else {
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softfloat_roundingMode = softfloat_round_near_even;
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//printf("argv[0] = %s arvg[1] = %s argv[2] = %s argv[3] = %s\n", argv[0], argv[1], argv[2], argv[3]);
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xn = parseNum(argv[1]);
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yn = parseNum(argv[3]);
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op1 = parseOp(argv[2]);
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@ -241,12 +308,22 @@ int main(int argc, char *argv[])
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r = f32_mulAdd(x, y, z);
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printF32("X", x); printF32("Y", y); printF32("Z", z);
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printF32("result = X*Y+Z", r); printFlags();
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} else { // opSize = 8
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} else if (opSize == 8) {
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float64_t x, y, z, r;
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x.v = xn; y.v = yn; z.v = zn;
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r = f64_mulAdd(x, y, z);
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printF64("X", x); printF64("Y", y); printF64("Z", z);
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printF64("result = X*Y+Z", r); printFlags();
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} else { // opSize = 16
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float128_t x, y, z, r;
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qp xc, yc, zc;
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xc.v = xn; yc.v = yn; zc.v = zn;
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x.v[0] = xc.v64[0]; x.v[1] = xc.v64[1];
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y.v[0] = yc.v64[0]; y.v[1] = yc.v64[1];
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z.v[0] = zc.v64[0]; z.v[1] = zc.v64[1];
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r = f128_mulAdd(x, y, z);
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printF128("X", x); printF128("Y", y); printF128("Z", z);
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printF128("result = X*Y+Z", r); printFlags();
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}
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}
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} else {
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@ -279,7 +356,7 @@ int main(int argc, char *argv[])
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sprintf(cmd, "0x%08x %c 0x%08x", x.v, op1, y.v);
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printF32(cmd, r); printFlags();
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} else { // opSize = 8
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} else if (opSize == 8) { // opSize = 8
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float64_t x, y, r;
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x.v = xn; y.v = yn;
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switch (op1) {
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@ -293,7 +370,25 @@ int main(int argc, char *argv[])
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printF64("X", x); printF64("Y", y);
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sprintf(cmd, "0x%016lx %c 0x%016lx", x.v, op1, y.v);
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printF64(cmd, r); printFlags();
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} else { // opSize = 16
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float128_t x, y, r;
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qp xc, yc;
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xc.v = xn; yc.v = yn;
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x.v[0] = xc.v64[0]; x.v[1] = xc.v64[1];
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y.v[0] = yc.v64[0]; y.v[1] = yc.v64[1];
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//x.v = xn; y.v = yn;
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switch (op1) {
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case 'x': r = f128_mul(x, y); break;
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case '+': r = f128_add(x, y); break;
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case '-': r = f128_sub(x, y); break;
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case '/': r = f128_div(x, y); break;
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case '%': r = f128_rem(x, y); break;
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default: printf("Unknown op %c\n", op1); exit(1);
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}
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printF128("X", x); printF128("Y", y);
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//sprintf(cmd, "0x%016lx %c 0x%016lx", x.v, op1, y.v);
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printF128(cmd, r); printFlags();
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printF128val(r);
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}
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}
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}
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@ -287,7 +287,7 @@ typedef struct packed {
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int LOGCVTLEN;
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int NORMSHIFTSZ;
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int LOGNORMSHIFTSZ;
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int CORRSHIFTSZ;
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int FMALEN;
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// division constants
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int LOGR ;
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@ -34,13 +34,13 @@ module fma import cvw::*; #(parameter cvw_t P) (
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input logic XZero, YZero, ZZero, // is the input zero
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input logic [2:0] OpCtrl, // operation control
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output logic ASticky, // sticky bit that is calculated during alignment
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output logic [3*P.NF+5:0] Sm, // the positive sum's significand
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output logic [P.FMALEN-1:0] Sm, // the positive sum's significand
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output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A)
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output logic As, // the aligned addend's sign (modified Z sign for other operations)
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output logic Ps, // the product's sign
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output logic Ss, // the sum's sign
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output logic [P.NE+1:0] Se, // the sum's exponent
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output logic [$clog2(3*P.NF+7)-1:0] SCnt // normalization shift count
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output logic [$clog2(P.FMALEN+1)-1:0] SCnt // normalization shift count
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);
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// OpCtrl:
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@ -54,8 +54,8 @@ module fma import cvw::*; #(parameter cvw_t P) (
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// 111 - sub
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logic [2*P.NF+1:0] Pm; // the product's significand in U(2.2Nf) format
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logic [3*P.NF+5:0] Am; // addend aligned's mantissa for addition in U(NF+4.2NF)
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logic [3*P.NF+5:0] AmInv; // aligned addend's mantissa possibly inverted
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logic [P.FMALEN-1:0] Am; // addend aligned's mantissa for addition in U(NF+4.2NF)
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logic [P.FMALEN-1:0] AmInv; // aligned addend's mantissa possibly inverted
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logic [2*P.NF+1:0] PmKilled; // the product's mantissa possibly killed U(2.2Nf)
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logic KillProd; // set the product to zero before addition if the product is too small to matter
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logic [P.NE+1:0] Pe; // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
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@ -89,6 +89,6 @@ module fma import cvw::*; #(parameter cvw_t P) (
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fmaadd #(P) add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ASticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
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fmalza #(3*P.NF+6, P.NF) lza(.A(AmInv), .Pm(PmKilled), .Cin(InvA & (~ASticky | KillProd)), .sub(InvA), .SCnt);
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fmalza #(P.FMALEN, P.NF) lza(.A(AmInv), .Pm(PmKilled), .Cin(InvA & (~ASticky | KillProd)), .sub(InvA), .SCnt);
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endmodule
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@ -31,14 +31,14 @@ module fmaalign import cvw::*; #(parameter cvw_t P) (
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input logic [P.NE-1:0] Xe, Ye, Ze, // biased exponents in B(NE.0) format
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input logic [P.NF:0] Zm, // significand in U(0.NF) format]
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input logic XZero, YZero, ZZero, // is the input zero
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output logic [3*P.NF+5:0] Am, // addend aligned for addition in U(NF+5.2NF+1)
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output logic [P.FMALEN-1:0] Am, // addend aligned for addition in U(NF+5.2NF+1)
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output logic ASticky, // Sticky bit calculated from the aliged addend
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output logic KillProd // should the product be set to zero
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);
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logic [P.NE+1:0] ACnt; // how far to shift the addend to align with the product in Q(NE+2.0) format
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logic [4*P.NF+5:0] ZmShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
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logic [4*P.NF+5:0] ZmPreshifted; // input to the alignment shifter U(NF+5.3NF+1)
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logic [P.FMALEN+P.NF-1:0] ZmShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
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logic [P.FMALEN+P.NF-1:0] ZmPreshifted; // input to the alignment shifter U(NF+5.3NF+1)
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logic KillZ; // should the addend be killed
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///////////////////////////////////////////////////////////////////////////////
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@ -56,7 +56,7 @@ module fmaalign import cvw::*; #(parameter cvw_t P) (
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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assign ZmPreshifted = {Zm,(3*P.NF+5)'(0)};
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assign ZmPreshifted = {Zm,(P.FMALEN-1)'(0)};
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assign KillProd = (ACnt[P.NE+1]&~ZZero)|XZero|YZero;
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assign KillZ = $signed(ACnt)>$signed((P.NE+2)'(3)*(P.NE+2)'(P.NF)+(P.NE+2)'(5));
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@ -87,6 +87,6 @@ module fmaalign import cvw::*; #(parameter cvw_t P) (
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end
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end
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assign Am = ZmShifted[4*P.NF+5:P.NF];
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assign Am = ZmShifted[P.FMALEN+P.NF-1:P.NF];
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endmodule
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@ -119,14 +119,14 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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// Fma Signals
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logic FmaAddSubE; // Multiply by 1.0 when adding or subtracting
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logic [1:0] FmaZSelE; // Select Z = Y when adding or subtracting, 0 when multiplying
|
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logic [3*P.NF+5:0] SmE, SmM; // Sum significand
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logic [P.FMALEN-1:0] SmE, SmM; // Sum significand
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logic FmaAStickyE, FmaAStickyM; // FMA addend sticky bit output
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logic [P.NE+1:0] SeE,SeM; // Sum exponent
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logic InvAE, InvAM; // Invert addend
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logic AsE, AsM; // Addend sign
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logic PsE, PsM; // Product sign
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logic SsE, SsM; // Sum sign
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logic [$clog2(3*P.NF+7)-1:0] SCntE, SCntM; // LZA sum leading zero count
|
||||
logic [$clog2(P.FMALEN+1)-1:0] SCntE, SCntM; // LZA sum leading zero count
|
||||
|
||||
// Cvt Signals
|
||||
logic [P.NE:0] CeE, CeM; // convert intermediate expoent
|
||||
@ -358,8 +358,8 @@ module fpu import cvw::*; #(parameter cvw_t P) (
|
||||
{XsE, YsE, XZeroE, YZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
|
||||
{XsM, YsM, XZeroM, YZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});
|
||||
flopenrc #(2) EMRegCmpFlg (clk, reset, FlushM, ~StallM, {PreNVE, PreNXE}, {PreNVM, PreNXM});
|
||||
flopenrc #(3*P.NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
|
||||
flopenrc #($clog2(3*P.NF+7)+7+P.NE) EMRegFma4(clk, reset, FlushM, ~StallM,
|
||||
flopenrc #(P.FMALEN) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
|
||||
flopenrc #($clog2(P.FMALEN+1)+7+P.NE) EMRegFma4(clk, reset, FlushM, ~StallM,
|
||||
{FmaAStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
|
||||
{FmaAStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
|
||||
flopenrc #(P.NE+P.LOGCVTLEN+P.CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM,
|
||||
|
||||
@ -51,7 +51,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
|
||||
|
||||
// Unbiased exponent
|
||||
assign E = Xe - P.BIAS[P.NE-1:0];
|
||||
assign Xep1 = Xe + 1;
|
||||
assign Xep1 = Xe + 1'b1;
|
||||
|
||||
//////////////////////////////////////////
|
||||
// Compute LSB L', rounding bit R' and Sticky bit T'
|
||||
@ -85,7 +85,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
|
||||
assign Lnonneg = |(Xm & HotE);
|
||||
assign Rnonneg = |(Xm & HotEP1);
|
||||
assign Trunc = Xm & IMask;
|
||||
assign {Two, Rnd} = Trunc + HotE; // Two means result is 10.000000 = 2.0
|
||||
assign {Two, Rnd} = Trunc + HotE; // Two means result overflowed to 10.000000 = 2.0
|
||||
|
||||
// mux and AND-OR logic to select final rounding bits
|
||||
mux2 #(1) Lmux(Lnonneg, 1'b0, Elt0, Lp);
|
||||
|
||||
@ -30,13 +30,13 @@
|
||||
module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [P.FMTBITS-1:0] Fmt, // precision 1 = double 0 = single
|
||||
input logic [P.NE+1:0] FmaSe, // sum's exponent
|
||||
input logic [3*P.NF+5:0] FmaSm, // the positive sum
|
||||
input logic [$clog2(3*P.NF+7)-1:0] FmaSCnt, // normalization shift count
|
||||
input logic [P.FMALEN-1:0] FmaSm, // the positive sum
|
||||
input logic [$clog2(P.FMALEN+1)-1:0] FmaSCnt, // normalization shift count
|
||||
output logic [P.NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account Subnormal or zero results
|
||||
output logic FmaSZero, // is the result subnormal - calculated before LZA corection
|
||||
output logic FmaSZero, // is the sum zero
|
||||
output logic FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection
|
||||
output logic [$clog2(3*P.NF+7)-1:0] FmaShiftAmt, // normalization shift count
|
||||
output logic [3*P.NF+7:0] FmaShiftIn // is the sum zero
|
||||
output logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt, // normalization shift count
|
||||
output logic [P.FMALEN+1:0] FmaShiftIn
|
||||
);
|
||||
logic [P.NE+1:0] PreNormSumExp; // the exponent of the normalized sum with the P.FLEN bias
|
||||
logic [P.NE+1:0] BiasCorr; // correction for bias
|
||||
@ -49,7 +49,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
|
||||
assign FmaSZero = ~(|FmaSm);
|
||||
|
||||
// calculate the sum's exponent FmaSe-FmaSCnt+NF+2
|
||||
assign PreNormSumExp = FmaSe + {{P.NE+2-$unsigned($clog2(3*P.NF+7)){1'b1}}, ~FmaSCnt} + (P.NE+2)'(P.NF+4);
|
||||
assign PreNormSumExp = FmaSe + {{P.NE+2-$unsigned($clog2(P.FMALEN+1)){1'b1}}, ~FmaSCnt} + (P.NE+2)'(P.NF+4);
|
||||
|
||||
//convert the sum's exponent into the proper precision
|
||||
if (P.FPSIZES == 1) begin
|
||||
@ -131,6 +131,6 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
|
||||
// set and calculate the shift input and amount
|
||||
// - shift once if killing a product and the result is subnormal
|
||||
assign FmaShiftIn = {2'b0, FmaSm};
|
||||
if (P.FPSIZES == 1) assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*P.NF+5)-1:0]+($clog2(3*P.NF+5))'(P.NF+3): FmaSCnt+1;
|
||||
else assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*P.NF+5)-1:0]+($clog2(3*P.NF+5))'(P.NF+3)+BiasCorr[$clog2(3*P.NF+5)-1:0]: FmaSCnt+1;
|
||||
if (P.FPSIZES == 1) assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3): FmaSCnt+1;
|
||||
else assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3)+BiasCorr[$clog2(P.FMALEN-1)-1:0]: FmaSCnt+1;
|
||||
endmodule
|
||||
|
||||
@ -44,9 +44,9 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
|
||||
input logic FmaPs, // the product's sign
|
||||
input logic FmaSs, // Sum sign
|
||||
input logic [P.NE+1:0] FmaSe, // the sum's exponent
|
||||
input logic [3*P.NF+5:0] FmaSm, // the positive sum
|
||||
input logic [P.FMALEN-1:0] FmaSm, // the positive sum
|
||||
input logic FmaASticky, // sticky bit that is calculated during alignment
|
||||
input logic [$clog2(3*P.NF+7)-1:0] FmaSCnt, // the normalization shift count
|
||||
input logic [$clog2(P.FMALEN+1)-1:0] FmaSCnt, // the normalization shift count
|
||||
//divide signals
|
||||
input logic DivSticky, // divider sticky bit
|
||||
input logic [P.NE+1:0] DivUe, // divsqrt exponent
|
||||
@ -70,8 +70,8 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
|
||||
logic Rs; // result sign
|
||||
logic [P.NF-1:0] Rf; // Result fraction
|
||||
logic [P.NE-1:0] Re; // Result exponent
|
||||
logic Ms; // norMalized sign
|
||||
logic [P.CORRSHIFTSZ-1:0] Mf; // norMalized fraction
|
||||
logic Ms; // normalized sign
|
||||
logic [P.NORMSHIFTSZ-1:0] Mf; // normalized fraction
|
||||
logic [P.NE+1:0] Me; // normalized exponent
|
||||
logic [P.NE+1:0] FullRe; // Re with bits to determine sign and overflow
|
||||
logic UfPlus1; // do you add one (for determining underflow flag)
|
||||
@ -86,10 +86,10 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
|
||||
// fma signals
|
||||
logic [P.NE+1:0] FmaMe; // exponent of the normalized sum
|
||||
logic FmaSZero; // is the sum zero
|
||||
logic [3*P.NF+7:0] FmaShiftIn; // fma shift input
|
||||
logic [P.FMALEN+1:0] FmaShiftIn; // fma shift input
|
||||
logic [P.NE+1:0] NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results
|
||||
logic FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection
|
||||
logic [$clog2(3*P.NF+5)-1:0] FmaShiftAmt; // normalization shift amount for fma
|
||||
logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt; // normalization shift amount for fma
|
||||
// division signals
|
||||
logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shif amount
|
||||
logic [P.NORMSHIFTSZ-1:0] DivShiftIn; // divsqrt shift input
|
||||
@ -154,8 +154,8 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
|
||||
always_comb
|
||||
case(PostProcSel)
|
||||
2'b10: begin // fma
|
||||
ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(3*P.NF+5){1'b0}}, FmaShiftAmt};
|
||||
ShiftIn = {FmaShiftIn, {P.NORMSHIFTSZ-(3*P.NF+8){1'b0}}};
|
||||
ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.FMALEN-1){1'b0}}, FmaShiftAmt};
|
||||
ShiftIn = {FmaShiftIn, {P.NORMSHIFTSZ-(P.FMALEN+2){1'b0}}};
|
||||
end
|
||||
2'b00: begin // cvt
|
||||
ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.CVTLEN+1){1'b0}}, CvtShiftAmt};
|
||||
|
||||
@ -32,7 +32,7 @@ module round import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [2:0] Frm, // rounding mode
|
||||
input logic [1:0] PostProcSel, // select the postprocessor output
|
||||
input logic Ms, // normalized sign
|
||||
input logic [P.CORRSHIFTSZ-1:0] Mf, // normalized fraction
|
||||
input logic [P.NORMSHIFTSZ-1:0] Mf, // normalized fraction
|
||||
// fma
|
||||
input logic FmaOp, // is an fma operation being done?
|
||||
input logic [P.NE+1:0] FmaMe, // exponent of the normalized sum for fma
|
||||
@ -123,61 +123,61 @@ module round import cvw::*; #(parameter cvw_t P) (
|
||||
// | NF |1|1|
|
||||
// ^ ^ if floating point result
|
||||
// ^ if not an FMA result
|
||||
if (XLENPOS == 1)assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]);
|
||||
if (XLENPOS == 1)assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.XLEN-2:0]);
|
||||
// 2: NF > XLEN
|
||||
if (XLENPOS == 2)assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&IntRes) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
|
||||
if (XLENPOS == 2)assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF-1]&IntRes) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
|
||||
|
||||
end else if (P.FPSIZES == 2) begin
|
||||
// XLEN is either 64 or 32
|
||||
// so half and single are always smaller then XLEN
|
||||
|
||||
// 1: XLEN > NF > NF1
|
||||
if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&FpRes&~OutFmt) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]);
|
||||
if (XLENPOS == 1) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&FpRes&~OutFmt) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.XLEN-2:0]);
|
||||
// 2: NF > XLEN > NF1
|
||||
if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~OutFmt) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&(IntRes|~OutFmt)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
|
||||
if (XLENPOS == 2) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&~OutFmt) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF-1]&(IntRes|~OutFmt)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
|
||||
// 3: NF > NF1 > XLEN
|
||||
if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&IntRes) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&(~OutFmt|IntRes)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
|
||||
if (XLENPOS == 3) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF1-1]&IntRes) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&(~OutFmt|IntRes)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
|
||||
|
||||
end else if (P.FPSIZES == 3) begin
|
||||
// 1: XLEN > NF > NF1
|
||||
if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&FpRes&~(OutFmt==P.FMT)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]);
|
||||
if (XLENPOS == 1) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF2-2:P.NORMSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&FpRes&~(OutFmt==P.FMT)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.XLEN-2:0]);
|
||||
// 2: NF > XLEN > NF1
|
||||
if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.FMT)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&(IntRes|~(OutFmt==P.FMT))) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
|
||||
if (XLENPOS == 2) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF2-2:P.NORMSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.FMT)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF-1]&(IntRes|~(OutFmt==P.FMT))) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
|
||||
// 3: NF > NF1 > XLEN
|
||||
if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT2)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT2)|IntRes)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&(~(OutFmt==P.FMT)|IntRes)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
|
||||
if (XLENPOS == 3) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF2-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT2)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT2)|IntRes)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&(~(OutFmt==P.FMT)|IntRes)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
|
||||
|
||||
end else if (P.FPSIZES == 4) begin
|
||||
// Quad precision will always be greater than XLEN
|
||||
// 2: NF > XLEN > NF1
|
||||
if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.H_NF-2:P.CORRSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.S_NF-2:P.CORRSHIFTSZ-P.D_NF-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.D_NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.Q_FMT)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.Q_NF-2:0]);
|
||||
if (XLENPOS == 2) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.H_NF-2:P.NORMSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.S_NF-2:P.NORMSHIFTSZ-P.D_NF-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.D_NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.Q_FMT)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.Q_NF-2:0]);
|
||||
// 3: NF > NF1 > XLEN
|
||||
// The extra XLEN bit will be ored later when caculating the final sticky bit - the ufplus1 not needed for integer
|
||||
if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.H_NF-2:P.CORRSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.S_NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.D_NF-1]&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT)|IntRes)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.D_NF-2:P.CORRSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.Q_NF-2:0]);
|
||||
if (XLENPOS == 3) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.H_NF-2:P.NORMSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.S_NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.D_NF-1]&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT)|IntRes)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.D_NF-2:P.NORMSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
|
||||
(|Mf[P.NORMSHIFTSZ-P.Q_NF-2:0]);
|
||||
|
||||
end
|
||||
|
||||
@ -188,32 +188,32 @@ module round import cvw::*; #(parameter cvw_t P) (
|
||||
// determine round and LSB of the rounded value
|
||||
// - underflow round bit is used to determint the underflow flag
|
||||
if (P.FPSIZES == 1) begin
|
||||
assign FpGuard = Mf[P.CORRSHIFTSZ-P.NF-1];
|
||||
assign FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF];
|
||||
assign FpRound = Mf[P.CORRSHIFTSZ-P.NF-2];
|
||||
assign FpGuard = Mf[P.NORMSHIFTSZ-P.NF-1];
|
||||
assign FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF];
|
||||
assign FpRound = Mf[P.NORMSHIFTSZ-P.NF-2];
|
||||
|
||||
end else if (P.FPSIZES == 2) begin
|
||||
assign FpGuard = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF-1] : Mf[P.CORRSHIFTSZ-P.NF1-1];
|
||||
assign FpLsbRes = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF] : Mf[P.CORRSHIFTSZ-P.NF1];
|
||||
assign FpRound = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF-2] : Mf[P.CORRSHIFTSZ-P.NF1-2];
|
||||
assign FpGuard = OutFmt ? Mf[P.NORMSHIFTSZ-P.NF-1] : Mf[P.NORMSHIFTSZ-P.NF1-1];
|
||||
assign FpLsbRes = OutFmt ? Mf[P.NORMSHIFTSZ-P.NF] : Mf[P.NORMSHIFTSZ-P.NF1];
|
||||
assign FpRound = OutFmt ? Mf[P.NORMSHIFTSZ-P.NF-2] : Mf[P.NORMSHIFTSZ-P.NF1-2];
|
||||
|
||||
end else if (P.FPSIZES == 3) begin
|
||||
always_comb
|
||||
case (OutFmt)
|
||||
P.FMT: begin
|
||||
FpGuard = Mf[P.CORRSHIFTSZ-P.NF-1];
|
||||
FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF];
|
||||
FpRound = Mf[P.CORRSHIFTSZ-P.NF-2];
|
||||
FpGuard = Mf[P.NORMSHIFTSZ-P.NF-1];
|
||||
FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF];
|
||||
FpRound = Mf[P.NORMSHIFTSZ-P.NF-2];
|
||||
end
|
||||
P.FMT1: begin
|
||||
FpGuard = Mf[P.CORRSHIFTSZ-P.NF1-1];
|
||||
FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF1];
|
||||
FpRound = Mf[P.CORRSHIFTSZ-P.NF1-2];
|
||||
FpGuard = Mf[P.NORMSHIFTSZ-P.NF1-1];
|
||||
FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF1];
|
||||
FpRound = Mf[P.NORMSHIFTSZ-P.NF1-2];
|
||||
end
|
||||
P.FMT2: begin
|
||||
FpGuard = Mf[P.CORRSHIFTSZ-P.NF2-1];
|
||||
FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF2];
|
||||
FpRound = Mf[P.CORRSHIFTSZ-P.NF2-2];
|
||||
FpGuard = Mf[P.NORMSHIFTSZ-P.NF2-1];
|
||||
FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF2];
|
||||
FpRound = Mf[P.NORMSHIFTSZ-P.NF2-2];
|
||||
end
|
||||
default: begin
|
||||
FpGuard = 1'bx;
|
||||
@ -225,31 +225,31 @@ module round import cvw::*; #(parameter cvw_t P) (
|
||||
always_comb
|
||||
case (OutFmt)
|
||||
2'h3: begin
|
||||
FpGuard = Mf[P.CORRSHIFTSZ-P.Q_NF-1];
|
||||
FpLsbRes = Mf[P.CORRSHIFTSZ-P.Q_NF];
|
||||
FpRound = Mf[P.CORRSHIFTSZ-P.Q_NF-2];
|
||||
FpGuard = Mf[P.NORMSHIFTSZ-P.Q_NF-1];
|
||||
FpLsbRes = Mf[P.NORMSHIFTSZ-P.Q_NF];
|
||||
FpRound = Mf[P.NORMSHIFTSZ-P.Q_NF-2];
|
||||
end
|
||||
2'h1: begin
|
||||
FpGuard = Mf[P.CORRSHIFTSZ-P.D_NF-1];
|
||||
FpLsbRes = Mf[P.CORRSHIFTSZ-P.D_NF];
|
||||
FpRound = Mf[P.CORRSHIFTSZ-P.D_NF-2];
|
||||
FpGuard = Mf[P.NORMSHIFTSZ-P.D_NF-1];
|
||||
FpLsbRes = Mf[P.NORMSHIFTSZ-P.D_NF];
|
||||
FpRound = Mf[P.NORMSHIFTSZ-P.D_NF-2];
|
||||
end
|
||||
2'h0: begin
|
||||
FpGuard = Mf[P.CORRSHIFTSZ-P.S_NF-1];
|
||||
FpLsbRes = Mf[P.CORRSHIFTSZ-P.S_NF];
|
||||
FpRound = Mf[P.CORRSHIFTSZ-P.S_NF-2];
|
||||
FpGuard = Mf[P.NORMSHIFTSZ-P.S_NF-1];
|
||||
FpLsbRes = Mf[P.NORMSHIFTSZ-P.S_NF];
|
||||
FpRound = Mf[P.NORMSHIFTSZ-P.S_NF-2];
|
||||
end
|
||||
2'h2: begin
|
||||
FpGuard = Mf[P.CORRSHIFTSZ-P.H_NF-1];
|
||||
FpLsbRes = Mf[P.CORRSHIFTSZ-P.H_NF];
|
||||
FpRound = Mf[P.CORRSHIFTSZ-P.H_NF-2];
|
||||
FpGuard = Mf[P.NORMSHIFTSZ-P.H_NF-1];
|
||||
FpLsbRes = Mf[P.NORMSHIFTSZ-P.H_NF];
|
||||
FpRound = Mf[P.NORMSHIFTSZ-P.H_NF-2];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
assign Guard = CvtToInt ? Mf[P.CORRSHIFTSZ-P.XLEN-1] : FpGuard;
|
||||
assign LsbRes = CvtToInt ? Mf[P.CORRSHIFTSZ-P.XLEN] : FpLsbRes;
|
||||
assign Round = CvtToInt ? Mf[P.CORRSHIFTSZ-P.XLEN-2] : FpRound;
|
||||
assign Guard = CvtToInt ? Mf[P.NORMSHIFTSZ-P.XLEN-1] : FpGuard;
|
||||
assign LsbRes = CvtToInt ? Mf[P.NORMSHIFTSZ-P.XLEN] : FpLsbRes;
|
||||
assign Round = CvtToInt ? Mf[P.NORMSHIFTSZ-P.XLEN-2] : FpRound;
|
||||
|
||||
always_comb begin
|
||||
// Determine if you add 1
|
||||
@ -296,7 +296,7 @@ module round import cvw::*; #(parameter cvw_t P) (
|
||||
assign RoundAdd = {(P.Q_NE+1+P.H_NF)'(0), FpPlus1&(OutFmt==P.H_FMT), (P.S_NF-P.H_NF-1)'(0), FpPlus1&(OutFmt==P.S_FMT), (P.D_NF-P.S_NF-1)'(0), FpPlus1&(OutFmt==P.D_FMT), (P.Q_NF-P.D_NF-1)'(0), FpPlus1&(OutFmt==P.Q_FMT)};
|
||||
|
||||
// trim unneeded bits from fraction
|
||||
assign RoundFrac = Mf[P.CORRSHIFTSZ-1:P.CORRSHIFTSZ-P.NF];
|
||||
assign RoundFrac = Mf[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.NF];
|
||||
|
||||
// select the exponent
|
||||
always_comb
|
||||
|
||||
@ -41,11 +41,11 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) (
|
||||
input logic FmaSZero,
|
||||
// output
|
||||
output logic [P.NE+1:0] FmaMe, // exponent of the normalized sum
|
||||
output logic [P.CORRSHIFTSZ-1:0] Mf, // the shifted sum after correction
|
||||
output logic [P.NORMSHIFTSZ-1:0] Mf, // the shifted sum after correction
|
||||
output logic [P.NE+1:0] Ue // corrected exponent for divider
|
||||
);
|
||||
|
||||
logic [P.CORRSHIFTSZ-1:0] CorrShifted; // the shifted sum after LZA correction
|
||||
logic [P.NORMSHIFTSZ-1:0] CorrShifted; // the shifted sum after LZA correction
|
||||
logic ResSubnorm; // is the result Subnormal
|
||||
logic LZAPlus1; // add one or two to the sum's exponent due to LZA correction
|
||||
logic LeftShiftQm; // should the divsqrt result be shifted one to the left
|
||||
@ -69,12 +69,12 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) (
|
||||
assign RightShift = FmaOp ? LZAPlus1 : LeftShiftQm;
|
||||
|
||||
// one bit right shift for FMA or division
|
||||
mux2 #(P.NORMSHIFTSZ-2) corrmux(Shifted[P.NORMSHIFTSZ-3:0], Shifted[P.NORMSHIFTSZ-2:1], RightShift, CorrShifted);
|
||||
mux2 #(P.NORMSHIFTSZ) corrmux({Shifted[P.NORMSHIFTSZ-3:0], 2'b00}, {Shifted[P.NORMSHIFTSZ-2:1], 2'b00}, RightShift, CorrShifted);
|
||||
|
||||
// if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits
|
||||
always_comb
|
||||
if (FmaOp | (DivOp & ~DivResSubnorm)) Mf = CorrShifted;
|
||||
else Mf = Shifted[P.NORMSHIFTSZ-1:2];
|
||||
else Mf = Shifted[P.NORMSHIFTSZ-1:0];
|
||||
|
||||
// Determine sum's exponent
|
||||
// main exponent issues:
|
||||
|
||||
@ -98,8 +98,8 @@ module testbench_fp;
|
||||
logic [P.NE+1:0] Se;
|
||||
logic ASticky;
|
||||
logic KillProd;
|
||||
logic [$clog2(3*P.NF+7)-1:0] SCnt;
|
||||
logic [3*P.NF+5:0] Sm;
|
||||
logic [$clog2(P.FMALEN+1)-1:0] SCnt;
|
||||
logic [P.FMALEN-1:0] Sm;
|
||||
logic InvA;
|
||||
logic NegSum;
|
||||
logic As;
|
||||
|
||||
4966
tests/fp/quad/fp_dataset.py
Executable file
4966
tests/fp/quad/fp_dataset.py
Executable file
File diff suppressed because it is too large
Load Diff
14
tests/fp/quad/fpdatasetgen.py
Executable file
14
tests/fp/quad/fpdatasetgen.py
Executable file
@ -0,0 +1,14 @@
|
||||
#!/usr/bin/python
|
||||
|
||||
from fp_dataset import *
|
||||
#coverpoints=ibm_b1(128, 128, 'fadd.q', 2) #ibm_b1(flen, iflen, opcode, ops)
|
||||
coverpoints=ibm_b2(128,128,'fadd.q',2) #ibm_b2(flen, iflen, opcode, ops, int_val = 100, seed = -1)
|
||||
#coverpoints=ibm_b2(32,32,'fadd.s',2) #ibm_b2(flen, iflen, opcode, ops,seed = -1)
|
||||
#print(coverpoints)
|
||||
#quad_precision_hex = "0x3ff00000000000000000000000000001" # Example quad precision hexadecimal value
|
||||
#quad_precision_dec = fields_dec_converter(128, quad_precision_hex)
|
||||
#print(quad_precision_dec)
|
||||
for cvpts in coverpoints:
|
||||
print(cvpts)
|
||||
print("\n")
|
||||
print(len(coverpoints))
|
||||
Loading…
Reference in New Issue
Block a user