74 Commits

Author	SHA1	Message	Date
Ross Thompson	a89a1e675c	Merge branch 'boot' into mergeBoot ... Merges Jacob's new sdc controller into wally.	2023-07-21 17:43:45 -05:00
Jacob Pease	380d96b359	Working new boot process. Buildroot package for sdc.	2023-07-20 14:15:59 -05:00
Ross Thompson	cc5d8fbf06	Updates for fpga.	2023-06-27 11:04:20 -05:00
Ross Thompson	0423d7df82	I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug.	2023-06-16 17:00:27 -05:00
Jacob Pease	40f81d5da6	The Vivado-RISC-V SDC works. Wally is now booting through it.	2023-05-26 15:42:33 -05:00
Jacob Pease	2839f4f41a	AHB triggers write, but AXI side doesn't update.	2023-04-18 15:23:22 -05:00
Ross Thompson	e490ab09cf	Updated to help debut Jacob's crossbar woes.	2023-04-11 14:22:42 -05:00
Jacob Pease	b796b1b492	Build doesn't work. AXI Crossbar has problems.	2023-04-06 16:01:58 -05:00
Ross Thompson	be0318209e	Updated fpga ila script.	2023-03-06 13:14:48 -06:00
Jacob Pease	85d789a7e0	AXI Crossbar is working. Fixed address width in generator script.	2023-02-22 15:13:16 -06:00
Jacob Pease	f2e4274c9c	Fixed debug signal names. Builds on the fpga. Bug in the crossbar.	2023-02-16 17:33:21 -06:00
Ross Thompson	ff7dc4f34a	fpga constraints updates	2023-02-07 15:22:14 -06:00
Ross Thompson	2fc47bab9c	More fixes for the debug2.xdc constraints.	2023-01-20 20:48:19 -06:00
Ross Thompson	61efb22db1	More fixes to fpga ila debugger.	2023-01-20 20:28:21 -06:00
Ross Thompson	e28ea2d630	Fixed fpga constraints.	2023-01-20 20:18:04 -06:00
Ross Thompson	0ed9811e31	Updated fpga constraints.	2023-01-20 20:16:33 -06:00
Ross Thompson	11c6106022	Repaired fpga debugger.	2023-01-20 15:26:52 -06:00
Ross Thompson	e0ec45489a	Updated constraints to remove DivBusyE.	2022-12-30 10:51:35 -06:00
Ross Thompson	138c3542db	Updated fpga constraints.	2022-12-24 10:21:16 -06:00
Ross Thompson	b5a85b55f1	Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. ... Generate WFIStallM in the privileged unit rather than generate in hazard. Cleaned up the hazard cause logic to be consistent across all causes.	2022-12-23 15:10:37 -06:00
Ross Thompson	6b105bd217	Renamed IFU and LSU stalls.	2022-12-22 21:56:33 -06:00
Ross Thompson	15042fc856	Updated fpga constraints.	2022-12-21 14:50:01 -06:00
Ross Thompson	3ee6ed8542	Updated fpga constraints	2022-12-15 16:45:55 -06:00
rachanaerra	10ff69efc1	updated constraints file	2022-12-05 15:05:21 -06:00
Ross Thompson	30b2bd263c	Updates to fpga constraints.	2022-11-09 13:52:36 -06:00
Jacob Pease	160ca366c8	Added PLIC signals for debugging on FPGA.	2022-10-25 13:57:09 -05:00
Ross Thompson	92ace4d8f7	Forget to include updated xdc file.	2022-10-24 13:51:21 -05:00
Ross Thompson	a008c61939	Updated debug2.xdc for interlock fsm changes.	2022-10-19 17:34:47 -05:00
Ross Thompson	16e10a4c5b	added new constraints for fpga.	2022-09-17 22:20:06 -05:00
Ross Thompson	787f5bcccb	Fixed fpga debug constraints.	2022-09-03 17:36:29 -05:00
Ross Thompson	4d60d9a840	Fixed up FPGA constraints. ... Added back in the fpga boot rom preload.	2022-09-02 13:54:35 -05:00
Ross Thompson	01a7718471	Added generate around ebu.	2022-08-25 09:24:13 -05:00
Ross Thompson	701324eeb8	Updated ila signals. ... Improve fpga wave config. added back in the fpga preload.	2022-08-25 09:03:29 -05:00
Ross Thompson	8180d1ade4	Updated fpga debugger to latest RTL version.	2022-08-19 17:13:36 -05:00
Ross Thompson	8b2491c169	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-19 16:39:28 -05:00
Ross Thompson	83bca570ae	Modified debugger for updated rtl.	2022-06-04 14:39:55 -05:00
Ross Thompson	1318f702cf	Added more debug signals to uart.	2022-05-21 19:47:40 -05:00
Ross Thompson	db85afcd2d	Added more plic debugging signals.	2022-05-21 14:04:08 -05:00
Ross Thompson	6cae5aa88f	Updated the fpga constraints.	2022-05-21 13:32:03 -05:00
Ross Thompson	9079e67aae	Updated fpga debugger.	2022-05-17 23:04:01 -05:00
Ross Thompson	51add16def	Updated debugger constraints.	2022-05-09 10:19:25 -05:00
Ross Thompson	c045e3afd8	Added back the instret counter to ILA.	2022-04-17 18:44:07 -05:00
Ross Thompson	82356342f0	Added another GPR to debugger.	2022-04-17 18:12:05 -05:00
Ross Thompson	c16dec88de	Increased uart baud rate to 230400. ... Added uart signals to debugger.	2022-04-17 15:23:39 -05:00
Ross Thompson	43a294dc88	Added signals to ila.	2022-04-07 21:09:50 -05:00
Ross Thompson	9db8471bf2	Added sp to ila.	2022-04-07 16:29:41 -05:00
Ross Thompson	5ef6cde52e	Added more ILA signals.	2022-04-02 16:39:45 -05:00
Ross Thompson	0340c0fd44	Added wave config ... added new signals to ILA.	2022-04-01 12:44:14 -05:00
Ross Thompson	cb945a6a6a	Added PLIC to ILA.	2022-03-31 16:44:49 -05:00
Ross Thompson	4f1258043d	Updated constraints file.	2022-03-30 17:48:44 -05:00