Rose Thompson
94a1ce32e7
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 17:48:34 -05:00
Rose Thompson
8ca565ed53
Updated for a better ILA rvvi debugger.
2024-07-22 17:44:04 -05:00
Jacob Pease
b05052311f
Added sd_cmd and utility SPI functions.
2024-07-22 16:57:04 -05:00
Rose Thompson
121342f4cc
Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
2024-07-22 16:12:06 -05:00
Jacob Pease
6a9141e3be
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-07-22 13:06:05 -05:00
Jacob Pease
cec39fd3aa
Added new SDC clock constraint.
2024-07-22 13:05:16 -05:00
Jacob Pease
a506d76149
Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
2024-07-22 12:36:39 -05:00
Rose Thompson
00c30239bf
Cleaned up rvvisynth.sv
2024-07-22 12:22:41 -05:00
Rose Thompson
556c210e76
Added option to use rvvi ila
2024-07-22 12:19:37 -05:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
32903a38f5
Merge pull request #890 from davidharrishmc/dev
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Fixed argument name in regression-wally
2024-07-22 12:00:25 -05:00
David Harris
4c46315907
Fixed argument name in regression-wally
2024-07-22 09:19:56 -07:00
Rose Thompson
844bc01c0a
Merge pull request #889 from davidharrishmc/dev
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Functional coverage improvements, fix WARL bug on MTVEC/STVEC
2024-07-22 10:59:16 -05:00
David Harris
040b359813
Added more RV64I coverage generation
2024-07-22 08:52:19 -07:00
Rose Thompson
24609f0b7f
Now have configurations to switch between supporting RVVI over ethernet.
2024-07-22 10:51:13 -05:00
David Harris
757cc8a5f7
Added QuestaFunctCoverage to merge functional coverage reports
2024-07-22 08:49:54 -07:00
David Harris
c4400dfeb0
Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode
2024-07-22 08:45:08 -07:00
Rose Thompson
d9ef588324
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-07-22 10:01:33 -05:00
Jacob Pease
e067e0896f
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-07-22 01:21:15 -05:00
Jacob Pease
e91d2c8b14
Corrected the CRC7 code with the right sequence of instructions.
2024-07-22 01:19:10 -05:00
David Harris
e949c9cfba
Removed more obsolete imperas scripts
2024-07-21 19:47:23 -07:00
David Harris
da502d2d5a
Fixed makefile log typo
2024-07-21 19:47:00 -07:00
David Harris
af79fd5702
Fixed hazard and rd_maxval coverage generation
2024-07-21 19:46:30 -07:00
David Harris
7fd8c6e29a
Removed outdated wally-imperas files
2024-07-21 19:45:22 -07:00
Jordan Carlin
5687e31c15
Merge pull request #888 from davidharrishmc/dev
2024-07-21 12:04:29 -07:00
Jordan Carlin
76fbb2e94d
Add --clean flag to install to remove git repositories and save space
2024-07-21 10:08:51 -07:00
Jordan Carlin
4ea5e3c4d4
Simplify version checking logic
2024-07-21 10:06:00 -07:00
David Harris
f30cc46ec5
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
Jacob Pease
c7d869bc96
Added inital spi based sd card code. Working on CRC7 code that works.
2024-07-20 14:00:43 -05:00
Jordan Carlin
37aa6acf5a
update riscof link
2024-07-20 01:36:33 -07:00
Jordan Carlin
0746f8fe89
Update opam installation to use /opt/riscv folder
2024-07-20 01:34:53 -07:00
Jordan Carlin
38c9c4749e
Use array of packages instead of string
2024-07-20 01:28:03 -07:00
Jordan Carlin
f68cb47a55
Use arithmetic comparisons where possible
2024-07-20 00:45:10 -07:00
Jordan Carlin
c3614aa189
Fix git_check function repo variable
2024-07-20 00:24:26 -07:00
Rose Thompson
00840e4893
Made the fpga top level configurable between rvvi synth and not.
2024-07-19 17:35:30 -05:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933
Cleanup in prep to merge the rvvi branch into main.
2024-07-19 15:48:20 -05:00
Rose Thompson
ce2cc48642
Updated verilog-ethernet to be compatible with wally.
2024-07-19 13:36:26 -05:00
Rose Thompson
a324e79b6f
Updated the ethernet frame gap for a faster computer.
2024-07-19 13:12:13 -05:00
Rose Thompson
9c1779a2d5
Added some documenation about sparse-checkout for verilog-ethernet submodule.
2024-07-19 13:11:48 -05:00
Jordan Carlin
a8848f02e8
Use apt-get to avoid warning about unstable apt interface
2024-07-19 11:09:27 -07:00
Jordan Carlin
f346a99907
Fix git_check return values
2024-07-19 11:09:27 -07:00
Jordan Carlin
6e4d6b7c07
Refactor git repo checks to use a function
2024-07-19 11:09:27 -07:00
Jacob Pease
53b2a51c89
Added tentative spi_send_byte function.
2024-07-19 12:30:32 -05:00
Jordan Carlin
954247af92
Update setup scripts to be more verbose about errors
2024-07-19 10:14:19 -07:00
Jordan Carlin
e30691d5e2
Add additional packages
2024-07-19 10:14:19 -07:00
Jacob Pease
34e89e842c
Added initial spi code to fpga/zsbl
2024-07-19 11:35:12 -05:00
Rose Thompson
e751fbe865
Merge pull request #887 from davidharrishmc/dev
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Fully decode decompressed instructions, including hints and illegal registers/immediates
2024-07-19 09:23:36 -05:00
David Harris
c64c12dc6c
Detect illegal compressed immediates, hints
2024-07-18 22:48:32 -07:00
David Harris
945722cd5b
Neatly formatted decompress.sv
2024-07-18 22:01:43 -07:00
