93 Commits

Author	SHA1	Message	Date
Jacob Pease	d8b75440b6	With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.	2024-08-20 16:24:37 -05:00
Jacob Pease	43b17b5058	Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose.	2024-08-20 14:40:50 -05:00
Jacob Pease	11a057b0b3	Updated wally source files for zsbl testing.	2024-08-02 15:33:57 -05:00
Jacob Pease	336a413f31	Added ability to split boot.memfile into boot.mem and data.mem.	2024-07-25 11:19:15 -05:00
Jacob Pease	f1cc7dd5a3	Fixed verilog bugs.	2024-07-23 17:26:39 -05:00
Jacob Pease	a506d76149	Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.	2024-07-22 12:36:39 -05:00
Ross Thompson	7f0ba87231	Updated comments in uart.	2024-06-19 13:51:30 -07:00
David Harris	cb563e8018	Clean up unused signals	2024-06-18 08:07:14 -07:00
David Harris	c1fd7a9589	Removed unused signals	2024-06-18 07:28:52 -07:00
David Harris	3fa37b0233	Lint cleanup	2024-06-18 06:15:17 -07:00
David Harris	7509e856df	Removed asynchronous reset causing lint issue in peripherals	2024-06-18 05:49:12 -07:00
David Harris	4a4bbdfc43	More code cleanup	2024-06-14 09:50:07 -07:00
David Harris	53477b2c85	Code cleanup	2024-06-14 07:08:17 -07:00
David Harris	8f09240e6c	Simplified outdated documentation pointers	2024-06-14 03:42:15 -07:00
David Harris	3f195884e9	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
David Harris	0419b5484a	parameterized register names in peripherals	2024-04-21 07:43:01 -07:00
slmnemo	39ae26a897	Added documentation for known Verilator hierarchy bug	2024-04-15 15:58:09 -07:00
slmnemo	4b80457f3e	Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory	2024-04-12 21:58:20 -07:00
David Harris	79cccfca82	Progress toward run_vcs	2024-04-03 14:05:07 -07:00
Kunlin Han	22b59138f0	Remove all #delay from non-testbench.	2024-03-16 11:20:32 -07:00
Kunlin Han	8c67a76912	Remove all #delay from non-testbench.	2024-03-13 10:31:40 -07:00
David Harris	e0eb91f795	Changed always @(posedge clk) to always_ff @(posedge clk) where it was omitted in several places	2024-03-06 11:02:04 -08:00
David Harris	b386331cc8	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00
David Harris	0abfe5cb55	Fixed some lint errors in derived configs	2024-01-31 11:39:59 -08:00
David Harris	f37c7bb1f6	Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this	2024-01-30 06:27:18 -08:00
David Harris	45e2317636	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
David Harris	6395cd0284	Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match	2023-12-21 12:29:37 -08:00
Rose Thompson	053b094620	Simpilified pmachecker for cmo.	2023-11-29 12:26:18 -06:00
Rose Thompson	beb95dd592	Modified the pmachecker to correctly check the permissions for cmo instructions. ... However this isn't fully tested.	2023-11-27 17:44:11 -06:00
David Harris	d3ce683e06	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
naichewa	8ffce456bd	Merge branch 'spi' into main	2023-11-14 14:51:06 -08:00
naichewa	1ab7c926ea	Final Code Review	2023-11-14 13:44:59 -08:00
Rose Thompson	95fc5f4a1c	Towards removing the FPGA config file.	2023-11-13 17:20:26 -06:00
Rose Thompson	a6995af91c	Fixed bug in uncore updates which broke SDC.	2023-11-13 16:15:23 -06:00
naichewa	5ce16dcb63	Cleanup	2023-11-09 16:52:55 -08:00
naichewa	3052a68d84	Remove old 2/4 bit logic, add comments, ... clean up unused signals	2023-11-09 16:48:11 -08:00
naichewa	b13b8feee4	updated to-do comments	2023-11-08 15:28:51 -08:00
naichewa	d67badfc60	fix hardware interlock, hold mode deassert	2023-11-08 15:20:51 -08:00
naichewa	a5837eb62c	fifo fixes and edge case testing	2023-11-07 17:59:46 -08:00
David Harris	4de21c206f	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-03 16:04:10 -07:00
David Harris	1f2899de14	Modified rams to take USE_SRAM rather than P to facilitate synthesis	2023-11-03 05:44:13 -07:00
naichewa	29e42b21df	added test cases	2023-11-02 15:42:28 -07:00
naichewa	e3d8162279	harris code review 3	2023-11-01 10:14:15 -07:00
naichewa	9aa8a7af3e	comments, more test cases	2023-11-01 01:26:34 -07:00
naichewa	fefb5adb8f	code review harris	2023-10-31 12:27:41 -07:00
naichewa	7dd3f24d6c	Merge branch 'main' into spi	2023-10-30 17:01:41 -07:00
naichewa	2330f4ee63	hardware interlock	2023-10-30 17:00:20 -07:00
David Harris	48d42c1e7c	Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates	2023-10-18 05:50:41 -07:00
naichewa	4941fe1769	sync fifo passes	2023-10-16 22:57:02 -07:00
naichewa	aa5abfc8e8	always working after reg bit swizzle changes	2023-10-13 14:22:32 -07:00