Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
2,376 Commits 5 Branches 2 Tags 53 MiB
d66f7c841b
Commit Graph

2376 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
David Harris
d66f7c841b Removed generate statements 2022-01-05 14:35:25 +00:00
Ross Thompson
98be8201b2 Renamed most signals inside cache.sv so they are agnostic to i or d. 2022-01-04 23:52:42 -06:00
Ross Thompson
fffaf654e6 the i and d caches now share common verilog. 2022-01-04 23:40:37 -06:00
Ross Thompson
13dbf3cc0f parameterized the caches with the goal of using common rtl for both i and d caches. 2022-01-04 22:40:51 -06:00
Ross Thompson
888a60d8d6 Switched block for line in caches. 2022-01-04 22:08:18 -06:00
Ross Thompson
cb301a78ad Fixed bug where last line of dcache was not written back to memory on dcache flush. 2022-01-04 21:55:48 -06:00
Ross Thompson
101a8bdb5b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-04 18:41:52 -06:00
Ross Thompson
ecc7bf5237 Fixed dcache flush. 2022-01-04 18:40:58 -06:00
David Harris
9ddc6db0a6 Removed imperas mmu tests; using wallypriv instead 2022-01-04 23:14:53 +00:00
Kip Macsai-Goren
04bcf5ef38 cleaned up Imperas tests to pass make 2022-01-04 21:32:21 +00:00
Kip Macsai-Goren
c65fc4d5e6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 21:30:51 +00:00
Kip Macsai-Goren
46b0cb810d fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh. 2022-01-04 21:30:38 +00:00
David Harris
0a7ec3e58d Fixed bad address for F/fmsub_b18-01 2022-01-04 21:04:06 +00:00
Kip Macsai-Goren
5218533ddc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 20:58:08 +00:00
David Harris
d1a7416028 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 19:47:51 +00:00
David Harris
115287adc8 Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
Kip Macsai-Goren
3a1f2befb1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 18:16:46 +00:00
Ross Thompson
f84200fee4 Added mmu tests to regression-wally. 
imperas64mmu passes but imperas32mmu does not.
 2022-01-04 11:13:36 -06:00
Ross Thompson
4fa19ae4c5 Modified dcache to ensure nontranslated index is used. 2022-01-04 10:53:53 -06:00
Kip Macsai-Goren
ac3bdc271f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 06:38:28 +00:00
Ross Thompson
63fb70fa61 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-03 23:49:28 -06:00
Ross Thompson
105763d938 Fixed icache stalling cpu when doing an uncached operation. 2022-01-03 23:49:19 -06:00
Kip Macsai-Goren
a763c37959 update 64 bit tests to make make work correctly and general cleanup 2022-01-04 05:02:33 +00:00
Kip Macsai-Goren
03e26f29a4 Update 32 bit memory tests to make make work correcttly and generally cleanup 2022-01-04 04:59:47 +00:00
Kip Macsai-Goren
e13c050fa1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 04:55:36 +00:00
Ross Thompson
2d1cb0c3a3 Reordered inputs/outputs in caches. 2022-01-03 22:52:50 -06:00
Ross Thompson
ff24718c28 Added generate around the spill logic so it is only used if supporting compressed instructions. 2022-01-03 22:23:04 -06:00
Ross Thompson
120a9d6a58 Minor improvement to icache. 2022-01-03 22:00:35 -06:00
Ross Thompson
89f4b920ff More Icache clean up. 2022-01-03 21:22:34 -06:00
Ross Thompson
2f7cb82c72 Major icache cleanup. 2022-01-03 21:12:17 -06:00
Ross Thompson
b045d84147 Removed spill support from icache. 2022-01-03 21:03:02 -06:00
Ross Thompson
8c7638688b The ifu now directly supports compressed without the icache providing the implemenation. 
The icache still constains all the orignal muxing logic to handle spills.  This should be removed.
 2022-01-03 20:49:47 -06:00
Ross Thompson
324362eee5 Almost working compressed instructions with compressed detection and processing in ifu rather than icache. 2022-01-03 18:10:15 -06:00
Ross Thompson
82fbc502e0 Prepared the ifu and icache for moving spills to ifu. 2022-01-03 17:09:36 -06:00
Ross Thompson
d77ddd2cbf Fixed bug with the icache. 2022-01-03 15:55:19 -06:00
Ross Thompson
c501276067 Fixed a bug where the instruction fetch got out of sync with the icache. 2022-01-03 13:27:15 -06:00
David Harris
95407a6ea7 Replaced && and || with & and | in non-fp files per new style guidelines 2022-01-02 21:47:21 +00:00
David Harris
77c00e996b Started adding asynchronous TIMECLK for CLINT 2022-01-02 21:18:16 +00:00
Katherine Parry
cf7aa4e8ae some errors in FP ArchTests fixed 2022-01-01 23:50:23 +00:00
David Harris
25dd532b6a Removed .* from MMU. 2021-12-31 07:19:51 +00:00
David Harris
272e884581 Removed .* from CSRs 2021-12-31 07:11:03 +00:00
David Harris
ae3767bd54 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-31 06:40:25 +00:00
David Harris
62e6aed7e5 Simplified performance counters 2021-12-31 06:40:21 +00:00
Ross Thompson
2096d45c23 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-30 18:10:36 -06:00
Ross Thompson
7055bfa4a7 Added mux to select between uncache instruction requests and cached instructions requests. 
Cacheless design almost works with the exception of compressed instructions.
 2021-12-30 18:09:37 -06:00
Ross Thompson
9432d9b72b Fixed wave.do. 2021-12-30 17:57:07 -06:00
Ross Thompson
89dc598a83 Patched up the linux-wave.do file. 2021-12-30 17:53:43 -06:00
David Harris
19a47bd276 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-30 23:40:02 +00:00
David Harris
4066ea6463 Fixes to counters; buildroot still broken 2021-12-30 23:39:59 +00:00
Ross Thompson
2a2db23803 Working without dcache. 2021-12-30 16:01:31 -06:00