Alec Vercruysse
d507f85190
icache coverage improvements by simplifying logic
2023-03-29 13:04:00 -07:00
Ross Thompson
d0f8db7939
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-28 16:31:50 -05:00
Ross Thompson
366a96a0fc
Possible fix for issue 148.
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I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Ross Thompson
e49cf8a028
Merge pull request #169 from davidharrishmc/dev
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PMP Fix to issue 132
2023-03-28 11:49:00 -05:00
David Harris
2e5c50e24a
Fixed RV32 tests after PMP fix
2023-03-28 08:35:23 -07:00
David Harris
e8904411ce
Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
2023-03-28 06:58:17 -07:00
David Harris
2e238c15aa
CSRS privileged coverage test
2023-03-28 04:37:56 -07:00
Ross Thompson
d91188c86e
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-27 11:55:19 -05:00
David Harris
9b7e5cec1f
Removed unnecessary monitor
2023-03-27 09:52:38 -07:00
Ross Thompson
d9691c1542
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-27 10:22:48 -05:00
Lee Moore
4bb7dadc00
Merge branch 'openhwgroup:main' into add-linux
2023-03-27 09:44:13 +01:00
Ross Thompson
ca4b058373
Modified plic and uart to remove async reset. This removes vivado critical warning.
2023-03-24 20:37:48 -05:00
Ross Thompson
0afba56927
Updated GPIO signal names to reflect book.
2023-03-24 18:55:43 -05:00
Ross Thompson
af8f1fd036
Renamed controllerinputstage to controllerinput to match book.
2023-03-24 17:57:02 -05:00
David Harris
0b0d954e7f
Merged ross's spacing fixes
2023-03-24 15:47:26 -07:00
David Harris
092d34373f
Merge pull request #159 from ross144/main
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Renamed signal to match book
2023-03-24 15:34:59 -07:00
Ross Thompson
46b1bca4fc
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
Ross Thompson
b5a58502d0
Replaced tabs -> spaces cache.
2023-03-24 15:15:38 -05:00
Ross Thompson
b518177a45
Updated EBU to replace tabs with spaces.
2023-03-24 15:01:38 -05:00
Kevin Kim
b70ab0fa5a
Zero/Sign extend mux in Shifter, Zero extend mux in Bitmanip alu
2023-03-24 11:52:51 -07:00
David Harris
4b9b20bce0
Shifter capitalization
2023-03-24 09:01:07 -07:00
Ross Thompson
47f8e847f0
Renamed ebu signal.
2023-03-24 10:51:04 -05:00
David Harris
89954df49b
Query about CondExtA
2023-03-24 08:35:33 -07:00
David Harris
21424d0f86
Shifter sign simplification and capitalization
2023-03-24 08:27:30 -07:00
David Harris
cb261731f2
FPU detect illegal instructions
2023-03-24 08:12:32 -07:00
David Harris
f1e87c5e69
Start of EBU coverage tests
2023-03-24 08:12:02 -07:00
David Harris
576545e328
ALUControl Elimination
2023-03-24 08:10:48 -07:00
David Harris
f648be8ee2
Merged ALUOp into ALUControl to simplify ALU mux
2023-03-24 07:28:42 -07:00
David Harris
89479391ca
Simplified rotate source to shifter
2023-03-24 06:49:26 -07:00
David Harris
e8d6073eca
BMU simplifications
2023-03-24 06:18:06 -07:00
David Harris
3bdb176253
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-24 05:59:48 -07:00
Kevin Kim
4c73f0fffd
minor formatting
2023-03-23 22:28:21 -07:00
Kevin Kim
5a19934511
comments
2023-03-23 22:22:25 -07:00
Kevin Kim
ae162a2694
removed redundant signals
...
-fixed some comments too
2023-03-23 22:20:37 -07:00
Kevin Kim
9c457e3af4
bitmanip alu submodule passes lint and regression
2023-03-23 21:56:03 -07:00
Kevin Kim
443e64bef2
more progress. Failing regression
2023-03-23 20:42:49 -07:00
Kevin Kim
2a2aa0470a
Merge branch 'openhwgroup:main' into bitmanip-alu
2023-03-23 19:53:50 -07:00
David Harris
c8ea5afe25
Removed unnecessary XZero from fdivsqrt
2023-03-23 17:25:59 -07:00
David Harris
f2864c7305
Merged BMU
2023-03-23 17:24:40 -07:00
Kevin Kim
8e67c64e2c
fixed rori rv32 bug
2023-03-23 16:06:46 -07:00
Kevin Kim
51d691215f
more progress on bitmanip alu modularization
2023-03-23 16:02:38 -07:00
David Harris
4e1bf6fbe0
Improved IEU and bitmanip test coverage
2023-03-23 14:24:41 -07:00
Kevin Kim
519a0452a5
started bitmanip alu modularization
2023-03-23 14:02:28 -07:00
David Harris
121d1cea62
Added csrwrites.S test case for privileged tests
2023-03-23 10:55:32 -07:00
Kevin Kim
a084b8ca31
Merge branch 'bit-manip' of https://github.com/kipmacsaigoren/cvw into bit-manip
2023-03-22 10:34:19 -07:00
Kevin Kim
fd00e386b5
remove outdated
2023-03-22 10:34:17 -07:00
Kevin Kim
1eb96e2221
Merge branch 'openhwgroup:main' into bit-manip
2023-03-22 10:33:15 -07:00
Kevin Kim
efa9f09864
updated header comments to indicate chapter 15
2023-03-22 10:31:21 -07:00
Kevin Kim
f7a915a71a
remove helper python script
2023-03-22 10:27:59 -07:00
Kevin Kim
fce62fc213
formatting
2023-03-22 10:26:04 -07:00
