David Harris
72d8d34e3c
allow all size memory access in CLINT; added underscore to peripheral address symbols
2021-06-18 08:05:50 -04:00
David Harris
91a13999a9
Added SUPPORTED to each peripheral in each config file
2021-06-17 21:36:32 -04:00
David Harris
09c5e27853
Started simplifying PMA checker
2021-06-17 16:28:06 -04:00
Katherine Parry
920ff984ca
Updated FMA
2021-06-14 13:42:53 -04:00
David Harris
79ee817d91
Reverted MIDELEG and MEDELEG to XLEN so busybear passes
2021-06-10 23:47:32 -04:00
bbracker
f0266f621b
merge
2021-06-10 10:03:01 -04:00
bbracker
31e1c926f2
attempt to fix regression by adding PMP_ENTRIES to configs
2021-06-10 09:59:26 -04:00
David Harris
17b76d4cd7
Configurable number of performance counters
2021-06-10 09:41:26 -04:00
David Harris
e231fc6b00
More verilator fixes, but bpred is broken
2021-06-09 21:03:03 -04:00
David Harris
3fb378dcf0
removed verilator lint_off WIDTH
2021-06-09 21:01:44 -04:00
David Harris
4bd7058456
More PMP entries
2021-06-08 15:33:06 -04:00
David Harris
9a17556de4
Start to parameterize number of PMP Entries
2021-06-08 15:29:22 -04:00
Kip Macsai-Goren
fcb9b1f0e1
working version with new mmu comments, old boottim values
2021-06-08 15:20:25 -04:00
David Harris
cfe5c27946
Resized BOOT TIM to 1 KB
2021-06-08 14:04:32 -04:00
David Harris
b37bcc8e38
Continued merge
2021-06-07 12:49:47 -04:00
David Harris
1e67db2f0c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
David Harris
95cc70295b
Merge difficulties
2021-06-07 09:50:23 -04:00
David Harris
8bbabb683d
Refactored configuration files and renamed testbench-busybear to testbench-linux
2021-06-07 09:46:52 -04:00
Kip Macsai-Goren
b99b5f8e0e
moved privilege dfinitions into wally-constants, upgraded relevant includes
2021-06-04 17:55:07 -04:00
David Harris
b836679ae1
Started MMU
2021-06-04 11:59:14 -04:00
David Harris
99d661cee9
Fixed RV32 MMU constants
2021-06-04 09:15:42 -04:00
David Harris
a61411995a
moved shared constants to a shared directory
2021-06-03 22:41:30 -04:00
Kip Macsai-Goren
06cf3a8403
Edited and added constants to support SV48
2021-06-01 17:49:45 -04:00
James E. Stine
bccdd2c137
Updates to muldiv.sv for 32-bit div/rem
2021-06-01 15:31:07 -04:00
Ross Thompson
9a49cf74c3
Changed to bp config to use gshare.
2021-06-01 12:14:58 -05:00
Ross Thompson
5bc2a8b346
Now have global history working correctly.
2021-06-01 10:57:43 -05:00
Ross Thompson
40bdcda32d
It's a bit sloppy, but the global history predictor is working correctly now.
...
There were two major bugs with the predictor.
First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome).
Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted.
This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow.
2021-05-27 23:06:28 -05:00
James E. Stine
474d479280
Update to rv64icfd wally-config to run through FP tests
2021-05-21 09:22:17 -05:00
Katherine Parry
71e4a10efb
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
James E. Stine
f407bee5ae
Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
2021-05-18 13:48:44 -05:00
Katherine Parry
409438bc95
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
Elizabeth Hedenberg
0fe798d5e1
pushing coremark to main branch
2021-05-11 21:33:39 -04:00
Shriya Nadgauda
0be6b81df9
finishing merge conflict changes
2021-05-03 22:15:05 -04:00
Shriya Nadgauda
52e0b703b7
merge conflict fixes
2021-05-03 22:12:30 -04:00
Shriya Nadgauda
0282aebec7
updated pipeline tests
2021-05-03 22:07:36 -04:00
Elizabeth Hedenberg
08bfaeffe3
coremark print statment
2021-05-03 19:35:08 -04:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
bbracker
0d62440f60
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-30 06:26:35 -04:00
bbracker
9c08ce5359
rv32 plic test and lint fixes
2021-04-30 06:26:31 -04:00
Ross Thompson
893e03d55b
Fixed memory size in configs for rv32ic and rv64ic.
...
Removed warning on call to $fscanf.
2021-04-29 17:36:46 -05:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Ross Thompson
44d28dbd1c
Icache integrated!
...
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
bbracker
5687ab1c96
do script refactor
2021-04-24 09:32:09 -04:00
bbracker
c796547156
greatly improved PLIC register interface
2021-04-22 11:22:01 -04:00
Noah Boorstin
c7a09d2359
yay buildroot passes a decent amount of tests now
...
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
2021-04-19 03:26:08 -04:00
Noah Boorstin
5902637632
buildroot: sim is now running!
...
yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9
start to add buildroot testbench
...
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
bbracker
11cf251378
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 21:09:27 -04:00
bbracker
195cead01c
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Domenico Ottolia
a149f2f3d8
Add support for vectored interrupts
2021-04-15 19:13:42 -04:00
Shreya Sanghai
75caa65df1
Cherry Pick merge of Shreya's localhistory predictor changes into main.
...
fixed minor bugs in localHistory
2021-04-15 09:04:36 -05:00
Shreya Sanghai
3696bf4f2c
fixed bugs in global history to read latest GHRE
...
Cherry pick Shreya's commits into main branch.
2021-04-15 08:55:22 -05:00
Thomas Fleming
e807f5d771
Implement support for superpages
2021-04-08 02:44:59 -04:00
Ross Thompson
d901cfc848
Merge branch 'icache_bp_bug' into tests
...
Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Ross Thompson
a5dc175ab2
Merge remote-tracking branch 'refs/remotes/origin/tests' into tests
2021-04-06 21:20:55 -05:00
Ross Thompson
0a20e33971
Steps to getting branch predictor benchmarks running.
2021-04-06 21:20:51 -05:00
bbracker
ce7b2314ef
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 06:40:53 -04:00
Thomas Fleming
06032936bd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-01 16:24:06 -04:00
Shreya Sanghai
bf3f4ff5b2
fixed minor bugs in localHistory
2021-04-01 13:40:08 -04:00
Shreya Sanghai
65e9747752
fixed bugs in global history to read latest GHRE
2021-03-31 21:56:14 -04:00
Teo Ene
6aed8eaea1
Updated MISA in coremark_bare config file
2021-03-31 20:39:02 -05:00
Ross Thompson
1e83810450
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-30 23:18:20 -05:00
Thomas Fleming
e3d548d452
Merge remote-tracking branch 'origin/main' into main
...
Bring icache and MMU code together
Conflicts:
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2
Complete basic page table walker
2021-03-30 22:19:27 -04:00
ushakya22
ba01d57767
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
Teo Ene
07f7df82e3
Added BPTYPE to coremark_bare config
2021-03-24 16:38:29 -05:00
Ross Thompson
c4f7c65210
updated the branch predictor config.
2021-03-23 13:54:59 -05:00
Ross Thompson
cebb2bc44d
Temporary exe2memfile0.pl script to support starting addresses of 0.
2021-03-23 13:54:59 -05:00
Ross Thompson
e6aef66853
Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses.
2021-03-23 13:54:59 -05:00
Noah Boorstin
4be19421c4
busybear: allow overwriting read values
2021-03-22 17:28:44 -04:00
bbracker
eea7e2e47e
first pass at PLIC interface
2021-03-22 10:14:21 -04:00
Shreya Sanghai
dfc86539cc
Merge branch 'gshare' into main
...
Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Ross Thompson
9386e6a524
Switched to gshare from global history.
...
Fixed a few minor bugs.
2021-03-18 16:05:59 -05:00
Noah Boorstin
847bf0b9a6
change ifndef to generate/if
2021-03-18 12:50:19 -04:00
Noah Boorstin
fa1407f6e3
everyone gets a bootram
2021-03-18 12:35:37 -04:00
Noah Boorstin
a226e24ed3
busybear: update memory map, add GPIO
2021-03-18 12:17:35 -04:00
Teo Ene
083a24c06b
addition to last commit
2021-03-17 14:52:31 -05:00
Elizabeth Hedenberg
74ebe0bef2
replicating coremark changes into coremark bare
2021-03-17 14:36:34 -04:00
Elizabeth Hedenberg
a3b2ffb2c9
Merge branch '3_3_2021' into main
...
Making sure coremark works with spring break changes
2021-03-17 14:11:37 -04:00
Noah Boorstin
162955de69
busybear: add COUNTERS define
2021-03-16 21:08:47 -04:00
Shreya Sanghai
d9b1e7d67f
added gshare and global history predictor
2021-03-16 17:03:01 -04:00
Shreya Sanghai
a79e26f9d8
added global history branch predictor
2021-03-16 16:06:40 -04:00
Shreya Sanghai
518618ad38
Merge branch 'counters' into main
...
added a configurable number of performance counters
2021-03-16 11:01:30 -04:00
Ross Thompson
8e51935082
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Thomas Fleming
e57b6cf18c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-03-11 00:15:58 -05:00
David Harris
bea8ac6d59
WALLY-LRSC atomic test passing
2021-03-09 09:28:25 -05:00
Ross Thompson
d6bc34121f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-05 15:27:22 -06:00
Ross Thompson
9a93193d6a
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
2021-03-05 15:23:53 -06:00
Thomas Fleming
ca2a65770c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 15:46:51 -05:00
Thomas Fleming
85dcbee86b
Place tlb parameters into constant header file
2021-03-05 13:35:24 -05:00
Noah Boorstin
0af002eb2f
busybear: make CSRs only weird for us
2021-03-05 00:46:32 +00:00
Shreya Sanghai
7cd8f1a592
added performance counters
2021-03-04 11:42:52 -05:00
Teo Ene
2723b21988
Linux CoreMark and baremetal CoreMark split into two separate tests/configs
2021-03-04 07:44:33 -06:00
Teo Ene
80f6d6c944
Linux CoreMark is operational
2021-03-04 05:58:18 -06:00
Teo Ene
0c009fb1e6
In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches
2021-03-04 01:27:05 -06:00
Noah Boorstin
f11b3108d8
busybear: fix bootram range
2021-03-01 17:45:21 +00:00
Noah Boorstin
2769b147cb
busybear: add 2nd dtim for bootram
2021-02-28 16:08:54 +00:00
Noah Boorstin
969c094489
busybear: remove gpio, start adding 2nd ram
2021-02-28 06:02:40 +00:00
Teo Ene
b9701293a0
Changed TIMBASE in coremark config file
2021-02-25 11:03:41 -06:00
