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d41b07aa85
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123 Commits

Author SHA1 Message Date
Cedar Turek
d41b07aa85 fpu idiv working on all configs with 1 copy of radix 2! 2022-12-26 23:18:28 -08:00
David Harris
71f214df20 Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
cturek
04bc787647 Added negative-result int diviison support in U and UM registers. 13 tests pass! 2022-12-22 16:25:37 +00:00
David Harris
954051da13 Removed CSR support from rv32i 2022-12-19 16:15:12 -08:00
Alessandro Maiuolo
3bcb42adb6 fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8) 2022-12-18 19:04:36 -08:00
David Harris
3bef12b108 Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE 2022-12-15 08:23:34 -08:00
David Harris
e80e84aace Added IDIV_ON_FPU flag to control whether integer division uses FPU 2022-12-15 06:37:55 -08:00
Ross Thompson
fa22484cfe Reverted the IROM/DTIM address range modelsim assignment. 2022-11-30 17:13:33 -06:00
cturek
f10700e666 Added A<B signal to fdivsqrt, started postprocessing merge 2022-11-13 22:40:26 +00:00
cturek
54f09f3616 Added conditional OTFC swap for simplified int postprocessing 2022-11-06 23:09:09 +00:00
cturek
83051a5351 Changed lzc names, started int/fp size merge in preproc 2022-11-06 22:21:35 +00:00
cturek
6bc4c1318e Added new macros for int div preprocessing, added p, n, and rightshiftx logic 2022-11-06 21:53:48 +00:00
cturek
9f41e57f03 Config Cleanup 2022-10-27 22:38:56 +00:00
cturek
71d16eacef unbroke DIVb 2022-10-26 16:11:51 +00:00
cturek
1febdb75b7 Config cleanup 2022-10-25 21:04:09 +00:00
Ross Thompson
dfd07a57fd Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults. 
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
 2022-10-11 10:47:13 -05:00
David Harris
31e9af0eb2 Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width 2022-10-10 09:10:55 -07:00
Ross Thompson
9d23b0e6d6 Reorganized the configs. 2022-10-09 16:46:48 -05:00
David Harris
29033dc334 Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests. 2022-10-05 11:46:52 -07:00
David Harris
f7d272c315 Gated sticky bit in fdiv with SpecialCase 2022-09-20 20:05:00 -07:00
David Harris
1cbdd20778 Restored radix 2 to pass regression 2022-09-20 19:30:16 -07:00
cturek
c3c764f0ba Fixed fgen4 2022-09-20 20:00:01 +00:00
David Harris
11fb39b373 Define LOGNORMSHIFTSZ 2022-09-20 08:31:57 -07:00
David Harris
73ceb4590c Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
David Harris
f38bb5b32e Divide testfloat starts with half-precision tests 2022-09-18 06:46:47 -07:00
David Harris
19e449b83d Fixed regression for divsqrt radix2 2022-09-07 06:12:23 -07:00
David Harris
09456db445 Checking in radix 4 square root with qsel, fgen, softc, but not working 2022-08-31 10:54:50 -07:00
David Harris
e1760dde55 Fixed checking termination in testfloat testbench 2022-08-30 10:55:21 -07:00
David Harris
4aa30c48aa fixed wally-config 2022-08-26 22:13:10 -07:00
David Harris
37f0b52520 Fixed address decoder hanging buildroot 2022-08-26 22:01:25 -07:00
David Harris
d0dbc74492 Fixed DTIM/IROM_BASE number of bits in buildroot/fpga configs 2022-08-26 21:29:26 -07:00
David Harris
2b241f8bbd Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding 2022-08-26 21:18:18 -07:00
David Harris
03e731b3ff Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM 2022-08-26 21:05:20 -07:00
David Harris
f0b4f69b65 Added IROM and DTIM decoding to adrdecs 2022-08-26 20:45:43 -07:00
David Harris
812158aeee Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
David Harris
95dd50a567 Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem 2022-08-26 20:12:03 -07:00
Ross Thompson
3b612d6201 Possible fixes for earily messup of rv32ic and rv64ic configs. 2022-08-25 14:42:08 -05:00
Ross Thompson
e605ef57dc BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
Ross Thompson
769af32f2a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
51adf6cba9 Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
e714b75888 LSU minor edits 2022-08-23 07:35:47 -07:00
Katherine Parry
36be692c0b sqrt passes - lint warnings remain 2022-08-22 17:16:12 +00:00
Katherine Parry
cb0c1b7488 radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
Katherine Parry
de6ae471bc fixed fsw problem and removed 2 bit shift from shift correction 2022-08-03 22:16:51 +00:00
Ross Thompson
69d520a7eb Removed replay from the config files. 2022-07-24 00:34:11 -05:00
Katherine Parry
b3d932cd61 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
Katherine Parry
fbe8bb2298 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
Katherine Parry
5cb9c9f319 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
cturek
cabd41a5a0 Six tests passing and a bunch of sizizing issues fixed 2022-07-14 19:38:27 +00:00
Katherine Parry
2fe8b6e34c fixed error in divsqrt 2022-07-14 18:16:00 +00:00