266 Commits

Author	SHA1	Message	Date
David Harris	d2282d5e87	Checked in fma16_template.v	2022-03-06 13:29:35 +00:00
David Harris	48705457d5	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
David Harris	545f569f78	Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas	2022-03-03 15:38:08 +00:00
David Harris	8fbdbba81a	fma file fixes	2022-03-02 23:47:01 +00:00
bbracker	be2f668867	but apparently QEMU doesn't show UXL in SSTATUS	2022-03-02 22:44:19 +00:00
bbracker	01e0f2f0d2	update SXL UXL bits in MSTATUS to match new QEMU trace	2022-03-02 22:15:57 +00:00
David Harris	3bea7bb431	removed imperas-riscv-tests	2022-03-02 17:28:20 +00:00
David Harris	1661983345	FMA project ready to start	2022-03-01 20:58:08 +00:00
David Harris	f314e60dc8	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
David Harris	f0a7ae2bba	adrdecs comments	2022-02-28 20:33:41 +00:00
David Harris	e108eb5195	Modified address decoder for native access to CLINT	2022-02-28 19:13:14 +00:00
David Harris	3519a20ccf	hptw cleanup for synthesis	2022-02-28 05:54:34 +00:00
David Harris	bb14dba9be	Created softfloat_demo showcasing how to do math with SoftFloat	2022-02-27 18:17:21 +00:00
David Harris	c7b5d32a72	Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior	2022-02-27 17:23:33 +00:00
David Harris	c6561d1e8b	Moved FMA back into source tree to facilitate synthesis	2022-02-27 15:41:41 +00:00
David Harris	274ecf13ad	Moved fma directory	2022-02-27 14:20:15 +00:00
David Harris	5a5142c14f	fma simulation infrastructure	2022-02-27 04:36:43 +00:00
David Harris	d917cc1379	fma passing multiply vectors	2022-02-27 04:36:01 +00:00
David Harris	8a55935456	simplified fma Makefile	2022-02-26 19:55:42 +00:00
David Harris	1852eccaab	Made softfloat.a a symlink	2022-02-26 19:53:04 +00:00
David Harris	87d1a8a1ac	Added start of fma	2022-02-26 19:51:19 +00:00
Ross Thompson	97d64201f7	Fixed bug with DAPageFault being wrong when HPTW writes not supported.	2022-02-23 10:54:34 -06:00
Ross Thompson	53f13d4cbc	More spillsupport more structual.	2022-02-23 10:27:14 -06:00
Ross Thompson	c23f6c7d90	Fixed bug with spill support and Instruction DA Page Faults.	2022-02-23 10:16:12 -06:00
Ross Thompson	62e1a97287	Added generates to pcnextf muxes for privileged and caches.	2022-02-22 22:45:00 -06:00
Ross Thompson	6a52f95cc8	Minor busdp cleanup.	2022-02-22 17:28:26 -06:00
Ross Thompson	59a2c09c5e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-22 14:45:53 -06:00
Ross Thompson	90be3d4360	Clarified interlockfsm.	2022-02-22 11:31:28 -06:00
bbracker	b8fd06576c	fix lint bugs in PLIC and UART	2022-02-22 05:04:18 +00:00
bbracker	a6047697c3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-22 04:27:50 +00:00
bbracker	e7934c585a	change RX side of UART to aslo be LSB-first	2022-02-22 03:34:08 +00:00
Ross Thompson	3a29504279	Added some clearity to lsuvirtmem.sv.	2022-02-21 17:20:58 -06:00
Ross Thompson	ca59778c5a	Annotated IFU for mux changes.	2022-02-21 17:20:34 -06:00
Ross Thompson	2f711fb642	Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.	2022-02-21 16:54:38 -06:00
Ross Thompson	0c65ea96d8	Cleaned up names in lsuvirtmem.	2022-02-21 16:44:30 -06:00
Ross Thompson	56fc6d0d7c	Minor cleanup of lsu.	2022-02-21 12:46:06 -06:00
Ross Thompson	f48b12b089	Moved mux into lsuvirtmem.	2022-02-21 09:31:29 -06:00
Ross Thompson	cbf4395457	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-21 09:06:09 -06:00
Ross Thompson	ae06785b9f	Minor changes to LSU.	2022-02-19 14:38:17 -06:00
David Harris	20a5798f43	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-18 23:08:47 +00:00
David Harris	6a0ffff05d	Removed problematic warning about reaching default state in HPTW	2022-02-18 23:08:40 +00:00
Ross Thompson	6cd9d84e7f	New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.	2022-02-17 17:19:41 -06:00
Ross Thompson	ad237b3ce5	Accidentally cleared dirty bit when setting access bit in hptw.	2022-02-17 16:20:20 -06:00
Ross Thompson	cbac34943c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-17 14:49:37 -06:00
Ross Thompson	0eec096474	Rough implementation passing regression test with hptw atomic writes to memory.	2022-02-17 14:46:11 -06:00
David Harris	f3c7025ade	Started make allsynth to try many experiments	2022-02-17 17:57:02 +00:00
Ross Thompson	2fc7dc3e57	Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.	2022-02-17 10:04:18 -06:00
Ross Thompson	62f5f1e622	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
Ross Thompson	c9e33208e3	Moved a few muxes around after sww changes.	2022-02-16 15:43:03 -06:00
Ross Thompson	71ed49bf2b	cleanup of signal names.	2022-02-16 15:29:08 -06:00