Katherine Parry
cf7aa4e8ae
some errors in FP ArchTests fixed
2022-01-01 23:50:23 +00:00
David Harris
ae3767bd54
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-31 06:40:25 +00:00
David Harris
62e6aed7e5
Simplified performance counters
2021-12-31 06:40:21 +00:00
Ross Thompson
9432d9b72b
Fixed wave.do.
2021-12-30 17:57:07 -06:00
Ross Thompson
89dc598a83
Patched up the linux-wave.do file.
2021-12-30 17:53:43 -06:00
Ross Thompson
bd531d1996
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-30 14:56:24 -06:00
Ross Thompson
59a38e3efd
Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.
2021-12-30 14:56:17 -06:00
Ross Thompson
9ea308b2d7
icache separated from bus fetch fsm. Does not work yet.
2021-12-30 14:23:05 -06:00
David Harris
91b8d7d2eb
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 17:22:22 +00:00
David Harris
e084c8868f
Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion
2021-12-30 17:22:18 +00:00
Ross Thompson
3803b9cd2d
Changed names of Icache signals.
2021-12-30 11:01:11 -06:00
Ross Thompson
e506957790
Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu.
2021-12-29 22:24:37 -06:00
David Harris
75b8e1f68e
Fixed lint for RV32IC by handling PMP_ENTRIES = 0 in csrm, but may have broken buildroot.
2021-12-30 02:38:42 +00:00
David Harris
26d6f8d51a
RV32ic tests running for simple machine with no privileged unit
2021-12-30 02:25:46 +00:00
David Harris
75c0c8ebea
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 00:53:44 +00:00
David Harris
866a5efc43
rv32i regression and linting
2021-12-30 00:53:39 +00:00
Ross Thompson
fd1c4b7313
Added default to busfsm.
2021-12-29 17:53:24 -06:00
Ross Thompson
87b7f80282
Moved lsu interlock fpm to separate module.
2021-12-29 17:40:24 -06:00
Ross Thompson
1955b6e740
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:35:45 -06:00
Ross Thompson
56d86f4dd5
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:12:29 -06:00
Ross Thompson
ac5746c721
Name cleanup in LSU.
2021-12-29 16:34:35 -06:00
Ross Thompson
aa227ce97c
Changed names of lsu address signals.
2021-12-29 15:03:34 -06:00
Ross Thompson
e36a037afa
Added more generates around virtual memory and csrs in the lsu.
2021-12-29 14:48:09 -06:00
Ross Thompson
5ebaeb5d90
Simplified the dcache to bus address generation.
2021-12-29 10:46:48 -06:00
Ross Thompson
15f1627a31
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
29b3285c8e
Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters.
...
Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
2021-12-28 21:28:03 -06:00
David Harris
40e0e6a401
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 00:29:12 +00:00
David Harris
d78b806332
Added performance counting to sumtest and added imperas32/64periph to testbench.
2021-12-29 00:28:51 +00:00
Ross Thompson
7044277165
Changed the bus name between dcache and ebu.
2021-12-28 15:57:36 -06:00
Ross Thompson
c1789932a4
Added generate around virtual memory hardware in LSU.
2021-12-28 15:00:02 -06:00
Ross Thompson
44b63fc0ba
First cut at moving the dcache bus interface into the LSU.
...
Regression test does not run and there is a lot of cleanup to do.
2021-12-27 18:12:59 -06:00
David Harris
52469db9ff
Added D and F tests to regression
2021-12-27 04:35:34 +00:00
David Harris
a7cfda8e52
Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.
2021-12-26 04:36:53 +00:00
David Harris
e97e512da9
Started FIR test code and started incorporating Imperas tests
2021-12-25 22:39:51 +00:00
David Harris
35e31006a9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-25 06:37:30 -08:00
David Harris
37b091e5da
Checked in Chapter 2 C and assembly examples
2021-12-25 06:35:36 -08:00
Ross Thompson
ae0cc085b4
Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.
...
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.
There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop
for each TLB line.
2021-12-23 12:40:22 -06:00
Ross Thompson
42ad710213
linux-wave.do changes.
2021-12-21 22:37:55 -06:00
Ross Thompson
47638cdccf
Looks like rdtime was accidentally replaced with rrame from a find and replace.
2021-12-20 21:26:38 -06:00
Ross Thompson
d830721a11
Fixed Type 5b interaction between dcache and hptw.
...
This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
82dd41a0fd
Rename of SelPTW to SelHPTW.
2021-12-19 22:24:07 -06:00
Ross Thompson
04d0b85f96
Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
2021-12-19 16:12:31 -06:00
Ross Thompson
9adcf86a40
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
...
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
0257c08641
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
fdf493bd47
minro change. comments about needed changes in dcache.
2021-12-19 13:53:02 -06:00
David Harris
da1df17fbb
Do File cleanups
2021-12-17 17:45:26 -08:00
David Harris
f4957fdac1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
David Harris
b42faa794a
changed ideal memory to MEM_DTIM and MEM_ITIM
2021-12-14 13:05:32 -08:00
David Harris
ee5c2e6101
renamed rv32/64g to rv32/64gc in configuration
2021-12-14 11:22:00 -08:00
David Harris
1ca949c0bb
Simplified ALU and source multiplexers pass tests
2021-12-13 07:57:38 -08:00
