Ross Thompson 59a38e3efd Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.		2021-12-30 14:56:17 -06:00
..
old
slack-notifier
wave-dos	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
buildrootBugFinder.py
fpga-wave.do	Do File cleanups	2021-12-17 17:45:26 -08:00
lint-wally	rv32i regression and linting	2021-12-30 00:53:39 +00:00
linux-wave.do	Changed names of lsu address signals.	2021-12-29 15:03:34 -06:00
make-tests.sh
Makefile	Started FIR test code and started incorporating Imperas tests	2021-12-25 22:39:51 +00:00
regression-wally.py	rv32i regression and linting	2021-12-30 00:53:39 +00:00
sim-buildroot
sim-buildroot-batch
sim-coremark-batch
sim-fp64
sim-fp64-batch
sim-wally	Started FIR test code and started incorporating Imperas tests	2021-12-25 22:39:51 +00:00
sim-wally-batch	Fixed lint for RV32IC by handling PMP_ENTRIES = 0 in csrm, but may have broken buildroot.	2021-12-30 02:38:42 +00:00
wally-buildroot-batch.do
wally-buildroot.do
wally-coremark.do	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
wally-fp64-batch.do
wally-fp64.do
wally-pipelined-batch.do
wally-pipelined-fpga.do	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
wally-pipelined.do
wave-all.do	Do File cleanups	2021-12-17 17:45:26 -08:00
wave-coremark.do	Do File cleanups	2021-12-17 17:45:26 -08:00
wave.do	Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.	2021-12-30 14:56:17 -06:00