cvw/wally-pipelined/regression
2021-12-21 22:37:55 -06:00
..
old
slack-notifier
wave-dos Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
buildrootBugFinder.py
fpga-wave.do Do File cleanups 2021-12-17 17:45:26 -08:00
lint-wally renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
linux-wave.do linux-wave.do changes. 2021-12-21 22:37:55 -06:00
make-tests.sh add buildroot tv linking to make-tests.sh 2021-12-07 11:15:59 -08:00
Makefile
regression-wally.py renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
sim-buildroot
sim-buildroot-batch
sim-coremark-batch Added coremark scripts to regression directory 2021-12-01 09:08:06 -08:00
sim-fp64
sim-fp64-batch renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
sim-wally changed ideal memory to MEM_DTIM and MEM_ITIM 2021-12-14 13:05:32 -08:00
sim-wally-batch Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
wally-buildroot-batch.do
wally-buildroot.do fix recursive signal logging for graphical sims 2021-12-08 16:07:26 -08:00
wally-coremark.do Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
wally-fp64-batch.do
wally-fp64.do renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
wally-pipelined-batch.do
wally-pipelined-fpga.do Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
wally-pipelined.do Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
wave-all.do Do File cleanups 2021-12-17 17:45:26 -08:00
wave-coremark.do Do File cleanups 2021-12-17 17:45:26 -08:00
wave.do Rename of SelPTW to SelHPTW. 2021-12-19 22:24:07 -06:00