Daniel Torres
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cf56a0d76a
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fixed issue where the unused spike elf files were being used to find objdump files that didn't exist causing makefile-memfile to fail prematurely
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2022-06-21 15:39:04 -07:00 |
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Madeleine Masser-Frye
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0161683945
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-21 20:31:06 +00:00 |
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Madeleine Masser-Frye
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fe31ee92e8
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switched comparator to dc flip version
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2022-06-21 20:30:33 +00:00 |
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James Stine
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493d3b1ac0
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Add hex output in bad but okay way
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2022-06-21 15:07:24 -05:00 |
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James Stine
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8e177b02e4
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Add MATLAB scripts for PD plot
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2022-06-21 10:14:53 -05:00 |
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slmnemo
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2b2760f5bd
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-21 02:16:26 -07:00 |
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slmnemo
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2b2ddbcc5e
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Added rudimentary GPIO test according to testplans in chapter 15
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2022-06-21 02:16:21 -07:00 |
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Katherine Parry
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edc15d6ef9
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made fixes to radix-2 divider testbench - divider doesn't pass
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2022-06-20 23:01:53 +00:00 |
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Katherine Parry
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5d5f79eb8f
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radix-4 divider passing tests
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2022-06-20 22:56:08 +00:00 |
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Katherine Parry
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254ebf478e
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added fld in rv32 - needs testing
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2022-06-20 22:53:13 +00:00 |
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James Stine
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1108268557
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Update C program for r=4 division by recurrence to match Table in EL
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2022-06-20 11:32:40 -05:00 |
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Daniel Torres
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d077199608
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embench and testbench now support running both O2 and Os build variations without overwriting one another
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2022-06-17 21:15:42 -07:00 |
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Daniel Torres
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1ef5ed8005
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arch tests now run on spike and sail and compare signatures during build
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2022-06-17 20:53:15 -07:00 |
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Daniel Torres
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dcdd3702c3
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removed old code from makefile, simplified code in testbench
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2022-06-17 15:13:38 -07:00 |
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Daniel Torres
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3a5c02b44a
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arch bug fixes and testbench changes
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2022-06-17 15:07:16 -07:00 |
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Katherine Parry
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8425f8838d
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hopefully fixed lint error
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2022-06-17 00:14:39 +00:00 |
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Katherine Parry
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93906b9457
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-15 22:58:42 +00:00 |
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Katherine Parry
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e121dcd4af
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postprocess out of fpu critical path
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2022-06-15 22:58:33 +00:00 |
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Madeleine Masser-Frye
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c2493168b6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-15 18:30:27 +00:00 |
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Madeleine Masser-Frye
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76e30ed8ab
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cleanup, plots for paper
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2022-06-15 18:28:36 +00:00 |
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James Stine
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d69a8f4077
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Add back SV for integer division to use 8-bit CPA in qslc
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2022-06-15 11:46:39 -05:00 |
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James Stine
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535a9a04ee
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Add r=4 C code
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2022-06-15 11:44:09 -05:00 |
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Katherine Parry
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11b252a735
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some synth fpu optimizations
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2022-06-14 23:58:39 +00:00 |
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Katherine Parry
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998876ce49
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removed false critical path from fpu
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2022-06-14 16:50:46 +00:00 |
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Katherine Parry
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566001e07b
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fixed acciedental critical path in FPU
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2022-06-14 00:02:38 +00:00 |
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DTowersM
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919c1818a8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 23:34:35 +00:00 |
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DTowersM
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1f4d56ba32
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added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
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2022-06-13 23:23:57 +00:00 |
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Katherine Parry
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31fd8772cf
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postprocessing unit created and passing all tests
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2022-06-13 22:47:51 +00:00 |
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David Harris
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8ea484a343
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Cleanup on RAM module
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2022-06-13 19:37:43 +00:00 |
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David Harris
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b7a7ca6eac
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Typo in gpio reset
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2022-06-13 19:37:05 +00:00 |
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slmnemo
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eb41185a70
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-13 12:30:33 -07:00 |
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David Harris
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be65e8f862
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Removed SRT testvectors from repo
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2022-06-13 19:27:33 +00:00 |
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slmnemo
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915b8e2adb
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-13 12:27:23 -07:00 |
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slmnemo
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7b704f8db0
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Merge branch 'cacheburstmode' into main.
Cache burst mode is now working! It also uses the new RAM.
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2022-06-13 12:26:18 -07:00 |
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slmnemo
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98c07ce2c0
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Added more comments
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2022-06-13 12:26:08 -07:00 |
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David Harris
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ccd16210bc
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 19:26:07 +00:00 |
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David Harris
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e9ef9a5cb8
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Fixed XOR logic in GPIO
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2022-06-13 19:26:03 +00:00 |
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slmnemo
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3d715a098c
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Added comment about name of LSUBusInit/Lock signal
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2022-06-13 10:56:02 -07:00 |
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slmnemo
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cadd62e49f
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Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
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2022-06-10 20:43:56 -07:00 |
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slmnemo
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beb4317e68
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Added comments to signals added so the bus is easier to analyze
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2022-06-10 20:30:04 -07:00 |
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slmnemo
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b7357efc6b
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Fixed failed regression state by only enabling counting when doing cached operations
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2022-06-10 20:00:09 -07:00 |
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slmnemo
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63ed390c90
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Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
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2022-06-10 19:10:01 -07:00 |
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Madeleine Masser-Frye
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422bd2043f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-10 21:11:47 +00:00 |
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Madeleine Masser-Frye
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7cdf9cd4d3
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added 'd' suffix to muxes for data-critical synths
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2022-06-10 21:11:05 +00:00 |
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DTowersM
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4bbe5eeecd
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simplified coremark
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2022-06-10 19:15:17 +00:00 |
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slmnemo
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dc11066ff2
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Passed Regression: Seems to work perfectly fine
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2022-06-09 18:21:13 -07:00 |
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slmnemo
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ec7cdee0f3
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Merge branch 'main' into cacheburstmode
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2022-06-09 17:51:03 -07:00 |
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slmnemo
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5a6eae214a
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?
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2022-06-09 17:50:47 -07:00 |
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DTowersM
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9e2d80764d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-10 00:38:07 +00:00 |
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DTowersM
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dd34f25ffd
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changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
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2022-06-10 00:37:53 +00:00 |
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