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Author	SHA1	Message	Date
Ross Thompson	abe57e3fd0	Added comment about better muxing.	2021-07-21 14:40:14 -05:00
Ross Thompson	3d79dc51bb	4 way set associative is now working.	2021-07-21 14:01:14 -05:00
Kip Macsai-Goren	e25b4643a8	removed remaining 32 bit loads/stores with 64 bit ones.	2021-07-21 14:45:22 -04:00
Kip Macsai-Goren	e59490d032	Fixed TLB parameterization and valid bit flop to correctly do instr page faults	2021-07-21 14:44:43 -04:00
Katherine Parry	59f79722ab	FDIV and FSQRT work	2021-07-21 14:08:14 -04:00
bbracker	e8b966c5d1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-21 13:04:11 -04:00
bbracker	f7a61a5c73	progress on recovering from QEMU's errors	2021-07-21 13:00:32 -04:00
Ross Thompson	39fc9278ba	Fixed remaining bugs in 2 way set associative dcache.	2021-07-21 10:35:23 -05:00
Ross Thompson	ba3aed8760	Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux. ... Also forgot to include cacheLRU.sv file.	2021-07-20 23:17:42 -05:00
Katherine Parry	61f81bb76e	FMA parameterized	2021-07-20 22:04:21 -04:00
Kip Macsai-Goren	53945adf4a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 21:04:53 -04:00
Kip Macsai-Goren	87e3f6c36d	light cleanup	2021-07-20 20:49:07 -04:00
Kip Macsai-Goren	f6bdb7b743	added new execution tests that should work with dcache memory non-syncness with 'real memory'. They make, but don't pass regression yet	2021-07-20 20:47:20 -04:00
Kip Macsai-Goren	e9fa2e18fd	added new executable test, cheange PTE to test library	2021-07-20 20:39:00 -04:00
Ross Thompson	8d0a552b5b	Partially working 2 way set associative d cache.	2021-07-20 17:51:42 -05:00
bbracker	d6c93a50aa	fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk	2021-07-20 17:55:44 -04:00
Kip Macsai-Goren	8521aecfa6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 17:01:09 -04:00
bbracker	b5ceb6f7c3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 15:04:13 -04:00
bbracker	945c8d496f	commented out old hack that used hardcoded addresses	2021-07-20 15:03:55 -04:00
David Harris	62b3673027	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 14:46:58 -04:00
David Harris	20744883df	flag for optional boottim	2021-07-20 14:46:37 -04:00
Ross Thompson	a042c356e1	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-20 13:27:58 -05:00
Ross Thompson	bb5b5e71b1	Replaced FinalReadDataM with ReadDataM in dcache.	2021-07-20 13:27:29 -05:00
Abe	38e24aacdd	Updated riscv64-unknown-elf-gcc location so that it can be easily accessed	2021-07-20 14:18:13 -04:00
bbracker	7694342d4e	ignore mhpmcounters because QEMU doesn't implement them	2021-07-20 13:37:52 -04:00
Kip Macsai-Goren	34d70426ce	Updated MMU tests to use shared library in assembly	2021-07-20 12:35:30 -04:00
bbracker	761300afcd	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 12:08:46 -04:00
David Harris	c117356432	Parameterized I$/D$ configurations and added sanity check assertions in testbench	2021-07-20 08:57:13 -04:00
bbracker	3de8461f3c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-20 05:40:49 -04:00
bbracker	c9775de3b2	testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)	2021-07-20 05:40:39 -04:00
James E. Stine	b36d6fe1be	slight mod to fpdiv - still bug in batch vs. non-batch	2021-07-20 01:47:46 -04:00
bbracker	5347a58192	major fixes to CSR checking	2021-07-20 00:22:07 -04:00
Ross Thompson	ae2371f2ce	Added performance counters for dcache access and dcache miss.	2021-07-19 22:12:20 -05:00
Ross Thompson	07c47f0034	Restored TIM range.	2021-07-19 21:17:31 -05:00
bbracker	a01fea69dd	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 19:30:40 -04:00
bbracker	af5d319f08	change debugBuildroot because GDB formatted list is now 50 lines long per instruction (we lost 6 CSRs on the whole)	2021-07-19 19:30:29 -04:00
David Harris	678f705415	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 18:19:59 -04:00
David Harris	b2f7952b3d	Added cache configuration to config files	2021-07-19 18:19:46 -04:00
bbracker	aeaf4a31f0	MemRWM shouldn't factor into PCD checking	2021-07-19 18:03:30 -04:00
bbracker	30c381c707	create qemu_output.txt	2021-07-19 18:02:41 -04:00
bbracker	45b78dd8b3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 17:11:49 -04:00
bbracker	5911029d2b	make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways	2021-07-19 17:11:42 -04:00
Kip Macsai-Goren	3a73ae0a8b	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 16:46:46 -04:00
bbracker	bb2e3b1e02	remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux	2021-07-19 16:22:05 -04:00
bbracker	78e513160e	put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests	2021-07-19 16:19:24 -04:00
bbracker	d603f4ea57	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 15:42:26 -04:00
bbracker	009e9d97bf	adapt testbench to removal of ReadDataWEn signal	2021-07-19 15:42:14 -04:00
bbracker	02de6014b2	adapt testbench to removal of signal	2021-07-19 15:41:50 -04:00
bbracker	76be84fa92	whoops MTIMECMP is always 64 bits	2021-07-19 15:40:53 -04:00
Abe	55391a8ef6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-19 15:20:38 -04:00