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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
Kip Macsai-Goren 2021-07-20 17:01:09 -04:00
commit 8521aecfa6
6 changed files with 30 additions and 28 deletions
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3
riscv-coremark/build-coremark.sh
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@ -4,7 +4,8 @@ set -e
BASEDIR=$PWD
CM_FOLDER=coremark
RISCV=/home/ehedenberg/riscvcompiler
#RISCV=/home/ehedenberg/riscvcompiler
RISCV=/courses/e190ax/riscvcompiler
XCFLAGS="-march=rv64im"
cd $BASEDIR/$CM_FOLDER

2
wally-pipelined/config/rv64ic/wally-config.vh
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@ -78,8 +78,6 @@
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
`define BOOTTIM_SUPPORTED 1'b1
//`define BOOTTIM_RANGE 56'h00003FFF
//`define BOOTTIM_BASE 56'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
`define BOOTTIM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
`define BOOTTIM_RANGE 56'h00000FFF
`define TIM_SUPPORTED 1'b1

9
wally-pipelined/src/cache/dcache.sv vendored
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@ -103,7 +103,7 @@ module dcache
logic [BLOCKLEN-1:0] ReadDataBlockM;
logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0];
logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0];
logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM, ReadDataWordMuxM;
logic [`XLEN-1:0] ReadDataWordM, ReadDataWordMuxM;
logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM;
logic [BLOCKLEN-1:0] FinalWriteDataWordsM;
logic [LOGWPL:0] FetchCount, NextFetchCount;
@ -309,7 +309,7 @@ module dcache
subwordread subwordread(.HRDATA(ReadDataWordMuxM),
.HADDRD(MemPAdrM[2:0]),
.HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}),
.HRDATAMasked(FinalReadDataWordM));
.HRDATAMasked(ReadDataM));
// This is a confusing point.
// The final read data should be updated only if the CPU's StallW is low
@ -324,10 +324,9 @@ module dcache
flopen #(`XLEN) ReadDataWReg(.clk(clk),
.en(~StallW),
.d(FinalReadDataWordM),
.d(ReadDataM),
.q(ReadDataW));
assign ReadDataM = FinalReadDataWordM;
// write path
subwordwrite subwordwrite(.HRDATA(ReadDataWordM),
@ -339,7 +338,7 @@ module dcache
generate
if (`A_SUPPORTED) begin
logic [`XLEN-1:0] AMOResult;
amoalu amoalu(.srca(FinalReadDataWordM), .srcb(WriteDataM), .funct(Funct7M), .width(Funct3M[1:0]),
amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(Funct3M[1:0]),
.result(AMOResult));
mux2 #(`XLEN) wdmux(FinalWriteDataM, AMOResult, SelAMOWrite & AtomicM[1], FinalAMOWriteDataM);
end else

2
wally-pipelined/src/uncore/uncore.sv
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@ -87,7 +87,7 @@ module uncore (
generate
// tightly integrated memory
dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*);
//if (`BOOTTIM_SUPPORTED) *** restore when naming is figured out
if (`BOOTTIM_SUPPORTED)
dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
// memory-mapped I/O peripherals

1
wally-pipelined/testbench/testbench-imperas.sv
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@ -753,6 +753,7 @@ module riscvassertions();
assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $error("Multiple Instruction Cache ways not yet implemented");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
assert (`TIM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if TIM_RANGE is less than 56'h07FFFFFF");
end
endmodule

41
wally-pipelined/testbench/testbench-linux.sv
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@ -27,7 +27,7 @@
module testbench();
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0675000; // # of instructions at which to turn on waves in graphical sim
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*2790000; // # of instructions at which to turn on waves in graphical sim
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
///////////////////////////////////////////////////////////////////////////////
@ -191,6 +191,9 @@ module testbench();
// Hack to compensate for QEMU's correct but different MTVAL (according to spec, storing the faulting instr is an optional feature)
if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,14) == "mtval") begin
force dut.hart.ieu.dp.WriteDataW = 0;
// Hack to compensate for QEMU's correct but different mhpmcounter's (these too are optional)
end else if (PCtextW.substr(0,3) == "csrr" && PCtextW.substr(10,20) == "mhpmcounter") begin
force dut.hart.ieu.dp.WriteDataW = 0;
end else release dut.hart.ieu.dp.WriteDataW;
end
end
@ -219,24 +222,24 @@ module testbench();
`SCAN_PC(data_file_PCF, scan_file_PCF, PCtextF, PCtextF2, InstrFExpected, PCFexpected);
`SCAN_PC(data_file_PCD, scan_file_PCD, PCtextD, PCtextD2, InstrDExpected, PCDexpected);
// NOP out certain instructions
if(dut.hart.ifu.PCD===PCDexpected) begin
if((dut.hart.ifu.PCD == 32'h80001dc6) || // for now, NOP out any stores to PLIC
(dut.hart.ifu.PCD == 32'h80001de0) ||
(dut.hart.ifu.PCD == 32'h80001de2)) begin
$display("warning: NOPing out %s at PCD=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time);
force InstrDExpected = 32'b0010011;
force dut.hart.ifu.InstrRawD = 32'b0010011;
while (clk != 0) #1;
while (clk != 1) #1;
release dut.hart.ifu.InstrRawD;
release InstrDExpected;
warningCount += 1;
forcedInstr = 1;
end else begin
forcedInstr = 0;
end
end
// NOP out certain instructions <-- commented out because no duh hardcoded addressses break easily
//if(dut.hart.ifu.PCD===PCDexpected) begin
// if((dut.hart.ifu.PCD == 32'h80001dc6) || // for now, NOP out any stores to PLIC
// (dut.hart.ifu.PCD == 32'h80001de0) ||
// (dut.hart.ifu.PCD == 32'h80001de2)) begin
// $display("warning: NOPing out %s at PCD=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time);
// force InstrDExpected = 32'b0010011;
// force dut.hart.ifu.InstrRawD = 32'b0010011;
// while (clk != 0) #1;
// while (clk != 1) #1;
// release dut.hart.ifu.InstrRawD;
// release InstrDExpected;
// warningCount += 1;
// forcedInstr = 1;
// end else begin
// forcedInstr = 0;
// end
//end
// Increment instruction count
if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||