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Configurable RISC-V Processor
1,510 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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Kip Macsai-Goren 53945adf4a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-20 21:04:53 -04:00
riscv-coremark
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wally-pipelined fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk 2021-07-20 17:55:44 -04:00
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.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
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README.md

riscv-wally

Configurable RISC-V Processor