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Configurable RISC-V Processor
1,486 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
b36d6fe1be
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James E. Stine b36d6fe1be slight mod to fpdiv - still bug in batch vs. non-batch
2021-07-20 01:47:46 -04:00
riscv-coremark Commented out remaining ehitoa function declaration/calls and related char buff instances. Also commented out extra libraries not currently in use 2021-07-14 04:46:11 -04:00
testsBP
wally-pipelined slight mod to fpdiv - still bug in batch vs. non-batch 2021-07-20 01:47:46 -04:00
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.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor