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1178 Commits

Author SHA1 Message Date
David Harris
2170203847 Simplified FPU-LSU interface to skip IEU 2022-08-22 13:28:51 -07:00
Katherine Parry
a1f0c6c598 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-22 17:16:25 +00:00
Katherine Parry
1accb92745 sqrt passes - lint warnings remain 2022-08-22 17:16:12 +00:00
David Harris
564281b8c1 Removed 2-cycle FPU-IEU latency stall 2022-08-22 16:14:15 +00:00
David Harris
1404d1c248 moved CSA to generic 2022-08-22 08:41:23 +00:00
David Harris
a8870b70b2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-22 08:28:31 +00:00
David Harris
b91f33372e Commented out unused comparators 2022-08-22 08:28:28 +00:00
Ross Thompson
88d34d0f56 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-21 16:03:11 -05:00
Ross Thompson
21526957cf Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
92c3cdc27d Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation. 2022-08-21 15:28:29 -05:00
Ross Thompson
a049f456e8 Removed logic from Verilog wrapper. 2022-08-21 14:07:43 -05:00
Ross Thompson
dad6770fc3 Updated fpga testbench. 2022-08-21 14:07:26 -05:00
Katherine Parry
617dc02d01 fixed -1 issue in division 2022-08-20 00:53:45 +00:00
Ross Thompson
96d6218078 Possible reduction of ignorerequest. 2022-08-19 18:07:44 -05:00
Ross Thompson
5301444a61 Changed signal names. 2022-08-17 16:12:04 -05:00
Ross Thompson
970a90dd72 Better name for LSUBusWriteCrit. Changed to SelLSUBusWord. 2022-08-17 16:09:20 -05:00
Ross Thompson
c3bd396bdb Removed old code from interlockfsm. 2022-08-17 12:52:56 -05:00
Katherine Parry
0f077012c3 sqrt tests in regression uncommented and pass 2022-08-07 23:38:10 +00:00
Katherine Parry
8eeca3319c radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
Katherine Parry
8f1d8669b0 fixed fsw problem and removed 2 bit shift from shift correction 2022-08-03 22:16:51 +00:00
David Harris
8b8f045491 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
6ee8036ae7 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
b13cdf79b3 FMA cleanup 2022-08-02 07:42:32 -07:00
David Harris
baeafc4fd2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-02 07:34:12 -07:00
David Harris
d3e39763b6 Moved InvA to sign block; simplified fmaexpadd coding 2022-08-02 07:34:09 -07:00
Ross Thompson
acd920ae2f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 22:09:11 -05:00
Ross Thompson
f7e64fcd69 Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
David Harris
0482bf4fc0 merged lza back into main 2022-08-01 19:45:21 -07:00
David Harris
0b95ca129c Fixed fmaadd to work with new LZA 2022-08-01 19:40:55 -07:00
Ross Thompson
b8356c7449 Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris. 2022-08-01 21:12:25 -05:00
Ross Thompson
171cf7413b Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask. 2022-08-01 21:08:14 -05:00
Ross Thompson
5d9dab6149 pulled swbbytemask out of subword write. 2022-08-01 20:48:45 -05:00
David Harris
8b44037f58 Parameterized fmalza 2022-08-01 16:18:02 -07:00
David Harris
6e78b46761 Completed LZA simplificaiton 2022-08-01 16:13:16 -07:00
David Harris
76021769a7 lza cleanup 2022-08-01 16:01:02 -07:00
David Harris
47d204f4a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-01 15:47:58 -07:00
David Harris
c8d4f3a542 lza cleanup 2022-08-01 15:47:03 -07:00
David Harris
c531df9c4e lza cleanup 2022-08-01 15:43:48 -07:00
David Harris
5468a90cf3 lza cleanup 2022-08-01 15:40:12 -07:00
David Harris
4953ccf273 lza cleanup 2022-08-01 15:37:09 -07:00
Katherine Parry
66eca28ccd regression passes fpu tests 2022-08-01 19:56:25 +00:00
Katherine Parry
9672f5451a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 19:55:50 +00:00
David Harris
31215277ee more lza cleanup 2022-08-01 12:34:00 -07:00
David Harris
48500c642c LZA cleanup 2022-08-01 12:30:42 -07:00
David Harris
87e6402af6 LZA refactoring switched to Pp1, Gm1, Km1 2022-08-01 12:20:23 -07:00
David Harris
5012b96120 LZA refactoring 2022-08-01 11:36:21 -07:00
Katherine Parry
75f39e0c5b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-01 18:35:07 +00:00
David Harris
231f52c1fd fmalza edits to match textbook 2022-08-01 18:23:39 +00:00
David Harris
e3b970d3ff Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
Ross Thompson
01359dbc4b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-31 12:48:51 -05:00
Katherine Parry
de03954946 re-added FStore2 in Cache 2022-07-29 22:54:49 +00:00
David Harris
d2de84a456 Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
David Harris
da275e3c26 Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
David Harris
ae4ea00ff0 fixed testbench merge comflict 2022-07-26 06:21:46 -07:00
David Harris
449c80b5f7 More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
094aacdf6f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-25 23:29:08 +00:00
David Harris
ccf8ccfa24 Added rv32f tests to RV64gc 2022-07-25 23:29:05 +00:00
David Harris
539174f6f6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
David Harris
55ab81e37b More riscof makefile tuning 2022-07-25 21:15:56 +00:00
David Harris
6b172723bd Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings 2022-07-25 20:50:38 +00:00
Ross Thompson
f1bd2524b7 Don't use this commit yet. Untested. 2022-07-24 15:40:52 -05:00
Ross Thompson
334008630f Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested. 2022-07-24 01:20:29 -05:00
Ross Thompson
856ac24686 Removed replay from the config files. 2022-07-24 00:34:11 -05:00
Ross Thompson
e12e6c3acd Added more i-cache signals to wave file. 2022-07-24 00:24:13 -05:00
Ross Thompson
458bfbf6f6 Merged evict dirty clear with flush write back. 2022-07-24 00:22:43 -05:00
Ross Thompson
70032bf8f4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Ross Thompson
5cd6c8069d signal name cleanup. 2022-07-22 23:36:27 -05:00
Ross Thompson
7d026e02f2 cache cleanup after removing replay on cpubusy. 2022-07-22 23:30:25 -05:00
Ross Thompson
706bc819e1 cache fsm cleanup after removal of replay. 2022-07-22 23:25:09 -05:00
Ross Thompson
0f586c9ed3 Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Katherine Parry
bd336f18b3 merged radix-2 sqrt into divider - doesnt work yet 2022-07-23 00:41:18 +00:00
slmnemo
5b71ceac5c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
0bfc3fda1b Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Daniel Torres
b726b05d61 fixed wally rv32e tests, updated regression makefile to new testflow 2022-07-22 17:09:46 -07:00
Katherine Parry
ee7932c804 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
Daniel Torres
d95b266d49 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
2bbfd67082 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
44c30ec082 fixed error in tests.vh 2022-07-22 14:55:55 -07:00
slmnemo
170601af0b Added UART test to peripheral test 2022-07-22 14:55:34 -07:00
Daniel Torres
fbe3a1af12 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 13:52:19 -07:00
Daniel Torres
261b9aa5a1 commented out embench test that should be commented out 2022-07-22 13:52:13 -07:00
slmnemo
49329b3f42 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 12:36:06 -07:00
slmnemo
0d98ff74b4 Added PLIC test to regression 2022-07-22 12:35:37 -07:00
Daniel Torres
5d7171f6f8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
526f70e772 commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
cturek
338f44dfc8 Square root negative exponent handling 2022-07-22 16:45:19 +00:00
slmnemo
49565f944c Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
David Harris
07c946bb04 Reset MSR on read 2022-07-22 04:29:27 +00:00
Daniel Torres
f1578936b8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-21 20:59:01 -07:00
Daniel Torres
bd918d37ba added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64 2022-07-21 20:58:58 -07:00
slmnemo
99dcff80c9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-21 20:35:52 -07:00
slmnemo
bfa500234d Fixed UART bug related to parity and MSR/LSR 2022-07-21 20:35:46 -07:00
cturek
c170a8d9b6 Changed testbench to operate on two inputs and one output, changed all test generators, changed srt module to return only one output and take in Mod as a signal to compute integer remainder 2022-07-22 01:27:08 +00:00
cturek
abe1ff906e Renamed variables, moved output handling to postprocessor, added remainder handling 2022-07-21 20:45:08 +00:00
Daniel Torres
a17361870f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-21 12:50:04 -07:00
Daniel Torres
6e9b4f4075 removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes 2022-07-21 12:47:51 -07:00
Katherine Parry
e330a840b0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-21 19:38:15 +00:00
Katherine Parry
270216dd02 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
cturek
ddc237f6bc Division working too 2022-07-21 17:59:10 +00:00
cturek
9c694b887e Updated Radix2 Sqrt to follow new algorithm 2022-07-21 17:36:21 +00:00