Ross Thompson 92c3cdc27d Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.		2022-08-21 15:28:29 -05:00
..
config	radix-2 1 copy passes testfloat	2022-08-06 22:54:05 +00:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Changed signal names.	2022-08-17 16:12:04 -05:00
src	Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.	2022-08-21 15:28:29 -05:00
srt	divider sizes reworked to match book	2022-07-22 22:02:04 +00:00
testbench	Updated fpga testbench.	2022-08-21 14:07:26 -05:00