Removed 2-cycle FPU-IEU latency stall

pipelined/src/ieu/datapath.sv

@@ -123,6 +123,7 @@ module datapath (
   flopenrc #(`XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);
   flopenrc #(5)     RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
 
+  // *** simplify WriteDataE in this merge
   // floating point interactions: fcvt, fp stores
   if (`F_SUPPORTED&(`LLEN>`XLEN)) begin:fpmux
     logic [`XLEN-1:0] IFCvtResultW;

pipelined/src/ieu/forward.sv

@@ -58,7 +58,7 @@ module forward(
 
   // Stall on dependent operations that finish in Mem Stage and can't bypass in time
   assign MatchDE = (Rs1D == RdE) | (Rs2D == RdE); // Decode-stage instruction source depends on result from execute stage instruction
-  assign FPUStallD = FWriteIntE & MatchDE; 
+  assign FPUStallD = 0; // FWriteIntE & MatchDE; // FPU to Integer transfers have single-cycle latency
   assign LoadStallD = (MemReadE|SCE) & MatchDE;  
   assign MDUStallD = MDUE & MatchDE; 
   assign CSRRdStallD = CSRReadE & MatchDE;