Removed logic from Verilog wrapper.

2025-02-11 06:05:49 +00:00 · 2022-08-21 14:07:43 -05:00 · 2022-08-21 14:07:43 -05:00 · a049f456e8
commit a049f456e8
parent dad6770fc3
1 changed files with 1 additions and 1 deletions
--- a/pipelined/src/wally/wallypipelinedsocwrapper.v
+++ b/pipelined/src/wally/wallypipelinedsocwrapper.v
@ -42,7 +42,7 @@ module wallypipelinedsocwrapper (
  output 	     HCLK, HRESETn,
  output [31:0]      HADDR,
  output [`AHBW-1:0] HWDATA,
-  output logic [`XLEN/8-1:0] HWSTRB,
+  output [`XLEN/8-1:0] HWSTRB,
  output 	     HWRITE,
  output [2:0] 	     HSIZE,
  output [2:0] 	     HBURST,