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4336 Commits

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Author SHA1 Message Date
David Harris
d6f1453275 Cleaned up otfc4 2022-09-19 00:58:20 -07:00
David Harris
309995a6e9 OTFC simplification 2022-09-19 00:51:56 -07:00
David Harris
59b6346a28 Removed unused otfc for Q 2022-09-19 00:43:27 -07:00
David Harris
e764d4322c fdiv cleanup 2022-09-19 00:32:34 -07:00
David Harris
cf0c20d489 Division working again for radix 2 with unified OTFC 2022-09-19 00:30:30 -07:00
David Harris
b636072914 Unified on-the-fly conversion working for radix 2; broke radix-4 division 2022-09-19 00:04:00 -07:00
David Harris
4dbe1035cb Added 2 bits to C to initialize properly 2022-09-18 22:44:22 -07:00
David Harris
f202eb0f6f Added 2 bits to C to initialize properly 2022-09-18 22:42:35 -07:00
David Harris
cff3c2535d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-18 21:27:36 -07:00
David Harris
498c053aab FP testbench 2022-09-18 21:27:21 -07:00
David Harris
f38bb5b32e Divide testfloat starts with half-precision tests 2022-09-18 06:46:47 -07:00
Ross Thompson
16e10a4c5b added new constraints for fpga. 2022-09-17 22:20:06 -05:00
Ross Thompson
57c366c1b2 Removed NonIROM and NonDTIM select signals from IFU and LSU. 2022-09-17 22:01:03 -05:00
Ross Thompson
cb34b7c98f Found the ahb burst bug. 
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests.  It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads.  The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads.  In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
 2022-09-17 20:30:01 -05:00
Kip Macsai-Goren
9821a50eaa added mstatus uxl, sxl bit tests (not tested in regression yet) 2022-09-18 00:11:29 +00:00
Kip Macsai-Goren
0cc7f5719c ported endianness tests to 32 bits (not tested in regression yet) 2022-09-18 00:10:29 +00:00
Kip Macsai-Goren
c5cbe43732 Fixed typos in existing endianness test 2022-09-18 00:09:52 +00:00
Kip Macsai-Goren
e6987524ab added full coverage of subword loads and stores to endianness test 2022-09-17 23:14:38 +00:00
David Harris
b74a68ff0f Reduced number of cycles required for lower-precision sqrt 2022-09-17 09:55:34 -07:00
David Harris
ac78823f6c Starting to adust number of cycles for division/sqrt 2022-09-17 05:58:59 -07:00
cturek
79addec27a Fixed j1 to align with new C reg 2022-09-16 02:15:48 +00:00
Kip Macsai-Goren
cc7d1c8ef9 Created initial endianness tests 2022-09-16 01:06:26 +00:00
David Harris
8f2b3b2387 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-15 12:49:21 -07:00
David Harris
94dca9194e renamed endianswap 2022-09-15 12:49:18 -07:00
Ross Thompson
38e114a6c0 Fixed subword read to work with bigendian. 2022-09-15 14:08:04 -05:00
David Harris
29d9ded25c FDIVSQRT cleanup 2022-09-15 09:10:57 -07:00
Ross Thompson
cea012a640 renamed multimanager to multicontroller. 2022-09-14 14:03:37 -05:00
Ross Thompson
bf6468a24c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-14 13:59:22 -05:00
cturek
da67e02392 Added shift for radix 4 sqrt 2022-09-14 17:34:24 +00:00
cturek
47d02db2eb Moved X-1 to preproc 2022-09-14 17:26:56 +00:00
cturek
fe77b5e37b Delete srt 2022-09-14 17:02:42 +00:00
cturek
4f3baea0fc removed unnecessary XZero from wsmux 2022-09-14 16:59:52 +00:00
David Harris
14bbd07e63 ZMerge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-14 09:42:17 -07:00
Ross Thompson
2c86badeb2 pipelining of fetch into evict AHB requests. 2022-09-13 17:51:55 -05:00
Ross Thompson
c7d3580637 Renamed signals in the LSU. 2022-09-13 11:47:39 -05:00
David Harris
1495305045 Removed unused signals 2022-09-12 11:35:35 -07:00
David Harris
7197a6de44 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 16:05:58 -07:00
David Harris
7639c05e51 Moved C to shift before rather than after using in an iteration 2022-09-08 16:05:53 -07:00
David Harris
7ba9b0b349 divsqrt comment cleanup 2022-09-08 15:40:42 -07:00
Ross Thompson
c4a7d3c147 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 17:15:46 -05:00
David Harris
5ea82cff33 CSA-based completion detection 2022-09-08 14:58:08 -07:00
Ross Thompson
7891d71c2a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 15:55:30 -05:00
Ross Thompson
7f1ae039b0 Optimization. Able to remove hptw address muxes from the E stage. 2022-09-08 15:51:18 -05:00
David Harris
a493b402cb ZMerge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 11:38:08 -07:00
David Harris
f326b18af6 embench cleaned up 2022-09-08 11:38:01 -07:00
Ross Thompson
0904951a8c Oups the ahbinterface.sv was accidentally named abhinterface.sv. 2022-09-08 13:21:37 -05:00
Ross Thompson
6e8d97e921 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 16:36:51 -05:00
Ross Thompson
f4e3036593 Oups fixed order of ending swap with mux between cache and fetch buffer. 2022-09-07 16:29:47 -05:00
David Harris
2d5e7827df Factored out aplusbeq0 unit 2022-09-07 11:36:35 -07:00
David Harris
c730ddf74a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 11:11:39 -07:00