David Harris
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cc9a2fc62d
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Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
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2022-10-10 10:22:12 -07:00 |
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David Harris
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31e9af0eb2
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Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
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2022-10-10 09:10:55 -07:00 |
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David Harris
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fde4832642
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Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing
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2022-10-10 07:12:37 -07:00 |
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David Harris
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c20bc13ead
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Changed SNPS license server
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2022-10-10 06:59:11 -07:00 |
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Ross Thompson
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4bf5245f75
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-09 16:46:51 -05:00 |
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Ross Thompson
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9d23b0e6d6
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Reorganized the configs.
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2022-10-09 16:46:48 -05:00 |
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David Harris
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04dc0ac02c
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New fdivsqrtqsel4cmp module based on comparators rather than table lookup
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2022-10-09 04:47:44 -07:00 |
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David Harris
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4f312ea2e7
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Moved shift into divsqrt stage and cleaned up comments
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2022-10-09 04:45:45 -07:00 |
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David Harris
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2aa43848f5
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fdivsqrt code cleanup
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2022-10-09 03:37:27 -07:00 |
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Ross Thompson
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6ff4abd4f7
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Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.
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2022-10-05 15:46:53 -05:00 |
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Ross Thompson
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28584e4cca
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Fixed wally32e.
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2022-10-05 15:37:01 -05:00 |
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Ross Thompson
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52a1d3dafe
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Name clarifications.
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2022-10-05 15:36:56 -05:00 |
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Ross Thompson
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aa09b1ef16
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Fixed bug with combined dtim+bus.
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2022-10-05 15:16:01 -05:00 |
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Ross Thompson
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98521d073f
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Possibly have working dtim + bus config.
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2022-10-05 15:08:20 -05:00 |
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Ross Thompson
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b01ee070bd
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Updated wavefile.
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2022-10-05 14:55:40 -05:00 |
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Ross Thompson
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bf6f0e7219
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Fixed bug in EBU.
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2022-10-05 14:51:12 -05:00 |
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Ross Thompson
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cabcb5e89e
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Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.
Don't use this commit as the rv32i tests are not passing.
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2022-10-05 14:51:02 -05:00 |
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Ross Thompson
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5e09d1cca7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-05 14:03:44 -05:00 |
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David Harris
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29033dc334
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Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests.
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2022-10-05 11:46:52 -07:00 |
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Ross Thompson
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ea70e1c598
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Optimized the ebu's beat counting.
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2022-10-05 10:58:23 -05:00 |
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Ross Thompson
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beb954ae27
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-04 17:39:26 -05:00 |
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Ross Thompson
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e0a7abbe50
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-04 17:39:14 -05:00 |
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Ross Thompson
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294645a49f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-04 17:38:49 -05:00 |
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Ross Thompson
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494f8b94f4
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Reordered the eviction and fetch in cache so it follows a more logical order.
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2022-10-04 17:36:07 -05:00 |
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Ross Thompson
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2d063bbb2d
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Updated constraints file to work with alternate uart.
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2022-10-04 17:35:44 -05:00 |
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Ross Thompson
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18e739befc
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Modified cache lru to not have the delayed write.
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2022-10-04 15:14:58 -05:00 |
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Kip Macsai-Goren
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c18c181fc0
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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Kip Macsai-Goren
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3f6d05f7a2
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addded renamed file
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2022-10-04 17:37:05 +00:00 |
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Kip Macsai-Goren
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9a0b98037b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-10-04 17:33:54 +00:00 |
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Kip Macsai-Goren
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fb464b9546
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Renamed endianswap to match module name
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2022-10-04 17:33:49 +00:00 |
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Ross Thompson
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0ed0c18aa1
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Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
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2022-10-02 16:21:21 -05:00 |
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Ross Thompson
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d08c29e3c5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-10-01 15:01:22 -05:00 |
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Ross Thompson
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41ab4850e1
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Disable IFU bus access on TrapM.
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2022-10-01 14:54:16 -05:00 |
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Ross Thompson
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e27fcb1577
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Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.
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2022-09-29 18:37:34 -05:00 |
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David Harris
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657f16dfd1
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Adding start signals for integer divider to fdivsqrt
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2022-09-29 16:30:25 -07:00 |
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Ross Thompson
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2c0132aa9c
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Renamed signals in EBU.
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2022-09-29 18:29:38 -05:00 |
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cturek
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e8a869e0e7
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Added integer inputs and flags to divsqrt
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2022-09-29 23:08:27 +00:00 |
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Ross Thompson
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58d597b614
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Simplification to EBU.
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2022-09-29 18:06:34 -05:00 |
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Ross Thompson
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d81af3bca8
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Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
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2022-09-29 11:54:03 -05:00 |
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Ross Thompson
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32449dfe97
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Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
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2022-09-28 17:39:51 -05:00 |
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Ross Thompson
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4db017dac3
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Possible fix for ifu/lsu arbiration issue.
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2022-09-27 17:24:35 -05:00 |
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Ross Thompson
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4062fe56c0
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Possible fix to the bus cache interaction.
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2022-09-27 11:34:33 -05:00 |
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Ross Thompson
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07bb11518e
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Found a hidden bug in the cache to bus fsm interlock.
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2022-09-26 17:41:30 -05:00 |
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Ross Thompson
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996c4ca8f2
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renamed ahbmulticontroller to ebu.
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2022-09-26 14:37:18 -05:00 |
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Ross Thompson
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8ed173a5f5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-26 12:49:16 -05:00 |
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Ross Thompson
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0fcc314d06
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Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
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2022-09-26 12:48:26 -05:00 |
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Kip Macsai-Goren
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e603973dff
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added xlen and endianness test edits. xlen passes but endinanness still won't make
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2022-09-26 05:03:19 +00:00 |
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Kip Macsai-Goren
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61745f9804
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added simple post processing script to give branch miss proportion in coremark log
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2022-09-26 04:51:04 +00:00 |
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David Harris
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713df785d1
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changed always_ff to always in sram1p1rw to fix testbench complaint
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2022-09-25 19:56:40 -07:00 |
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Ross Thompson
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38edbde966
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Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
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2022-09-23 11:46:53 -05:00 |
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