Ross Thompson
51408c620e
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
d6f907f444
Sort of solved the bit width warning for dtim, irom ranges.
2022-10-19 10:42:19 -05:00
David Harris
aa5fe52407
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-14 17:33:36 -07:00
David Harris
51b702fa17
Removed unused FPU waves
2022-10-14 17:33:32 -07:00
Ross Thompson
22603464ae
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
dfd07a57fd
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
David Harris
cc9a2fc62d
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
31e9af0eb2
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
Ross Thompson
9d23b0e6d6
Reorganized the configs.
2022-10-09 16:46:48 -05:00
Ross Thompson
b01ee070bd
Updated wavefile.
2022-10-05 14:55:40 -05:00
Kip Macsai-Goren
9a0b98037b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
fb464b9546
Renamed endianswap to match module name
2022-10-04 17:33:49 +00:00
Ross Thompson
2c0132aa9c
Renamed signals in EBU.
2022-09-29 18:29:38 -05:00
David Harris
46680b80a7
Eliminated store after store stall when no cache; simplified divshiftcalc logic.
2022-09-21 13:02:34 -07:00
Ross Thompson
ac864a6ca3
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
...
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
David Harris
653c458241
Moved fpu modules into subdirectories
2022-09-20 04:12:05 -07:00
David Harris
59b6346a28
Removed unused otfc for Q
2022-09-19 00:43:27 -07:00
Ross Thompson
cea012a640
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
c7d3580637
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
David Harris
c730ddf74a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 11:11:39 -07:00
David Harris
7a29f9c95b
Running 16-bit square root cases first in testfloat
2022-09-07 11:11:35 -07:00
Ross Thompson
0615798467
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 12:26:50 -05:00
Ross Thompson
83306ec238
Named change for ahb tests to be less annoying.
2022-09-07 12:24:41 -05:00
Ross Thompson
3571fb18c2
Modified regression tests to add some ahb configurations.
2022-09-07 12:03:58 -05:00
David Harris
dff9416a33
Added rv32i config for regression of wally32periph
2022-09-07 09:37:59 -07:00
Ross Thompson
5a0cda9860
Merge branch 'multimanager' into main
2022-09-07 10:54:27 -05:00
David Harris
19e449b83d
Fixed regression for divsqrt radix2
2022-09-07 06:12:23 -07:00
Ross Thompson
c87268baf1
Modified ram_ahb to work with different latencies.
2022-09-04 14:46:15 -05:00
David Harris
5e26bcced1
Fixed lint errors in square root and improved waveforms in testfloat
2022-09-01 15:49:13 -07:00
Ross Thompson
f2f1169a04
Renamed AHBCachebusdp to abhcacheinterface.
2022-08-31 14:12:19 -05:00
Ross Thompson
f3d611c686
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-31 11:38:29 -05:00
Ross Thompson
5409501ca6
Maybe fixed it?
2022-08-30 18:08:34 -05:00
Ross Thompson
cce3fdd0e3
Updates to wave file.
2022-08-30 17:34:36 -05:00
Ross Thompson
8b9f30c91a
more progress.
2022-08-30 17:32:32 -05:00
Ross Thompson
fab3a2b791
Temporary commit.
2022-08-30 15:40:42 -05:00
Ross Thompson
315f662eb9
More progress.
2022-08-30 15:27:19 -05:00
Ross Thompson
637d60b64c
Progress.
2022-08-30 14:17:00 -05:00
David Harris
e1760dde55
Fixed checking termination in testfloat testbench
2022-08-30 10:55:21 -07:00
David Harris
7d4e85bf21
Separated out radix 2 and radix 4 stages into different modules
2022-08-29 04:26:14 -07:00
David Harris
2788022c22
renamed srt to fdivsqrt
2022-08-29 04:04:05 -07:00
David Harris
f2517f8290
Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
2022-08-27 20:31:09 -07:00
David Harris
60b673cafd
Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus
2022-08-27 05:31:56 -07:00
David Harris
37f0b52520
Fixed address decoder hanging buildroot
2022-08-26 22:01:25 -07:00
Ross Thompson
3b612d6201
Possible fixes for earily messup of rv32ic and rv64ic configs.
2022-08-25 14:42:08 -05:00
Ross Thompson
b0aea77b20
Added generate around uncore.
2022-08-25 10:35:24 -05:00
Ross Thompson
01a7718471
Added generate around ebu.
2022-08-25 09:24:13 -05:00
Ross Thompson
d10edfa5e0
No longer need wally-pipelined-fpga.do.
2022-08-24 18:10:45 -05:00
Ross Thompson
fc22e807e2
Merged testbench-fpga into testbench.
...
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
2022-08-24 17:52:25 -05:00
Ross Thompson
517c0f6c35
Changed signal names.
2022-08-17 16:12:04 -05:00
Katherine Parry
cb0c1b7488
radix-2 1 copy passes testfloat
2022-08-06 22:54:05 +00:00
