cturek
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cc6f219bdd
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Added A Sign register. Fixed postprocessing logic for postinc and rem calculation.
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2022-12-24 06:46:52 +00:00 |
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Ross Thompson
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b0d6c9616e
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Minor optimizations.
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2022-12-23 20:11:36 -06:00 |
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Ross Thompson
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6e9d1eb180
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-23 19:51:23 -06:00 |
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Katherine Parry
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4b50ffac91
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reworked negitive sticky bit handeling in fma
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2022-12-23 17:01:34 -06:00 |
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Ross Thompson
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6f9e21d61b
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Improved comment.
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2022-12-23 15:13:15 -06:00 |
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Ross Thompson
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a2de53aeeb
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Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
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2022-12-23 15:10:37 -06:00 |
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Ross Thompson
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fe9361de34
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Removed XEnE, YEnE, and ZEnE from forward logic.
Cleanup comments.
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2022-12-23 14:27:03 -06:00 |
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Ross Thompson
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af9afafdae
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Cleanup floating point hazard logic.
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2022-12-23 14:21:47 -06:00 |
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Ross Thompson
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b4c7998ded
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DON'T USE. First commit in attempt to move fpustall detection into the decode stage.
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2022-12-23 12:47:18 -06:00 |
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Ross Thompson
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f6f66cb79e
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Removed ZForwardEnE and replaced with ZEnE.
Similar for YForwardEnE.
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2022-12-23 12:27:51 -06:00 |
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Ross Thompson
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ca67e5588d
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Removed unnecessary stall when MatchDE was driven 1 by RdE == 0.
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2022-12-23 11:45:42 -06:00 |
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David Harris
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f038494760
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Commented out fdiv early termination - broke fsqrt test
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2022-12-23 00:58:55 -08:00 |
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David Harris
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e061bacc9d
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Fixed early termination on fdivsqrt
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2022-12-23 00:53:55 -08:00 |
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David Harris
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0505f1fd37
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Moved InstrValidNotFLushed to csr including InstrValidM
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2022-12-23 00:27:44 -08:00 |
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David Harris
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3b1fe78bdc
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Removed unused StallW from CSRs
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2022-12-23 00:21:36 -08:00 |
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David Harris
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9e21358d75
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Removed unused signals from FPU
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2022-12-23 00:18:39 -08:00 |
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David Harris
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0a7ed944a5
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Revert to 98b824
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2022-12-22 23:58:14 -08:00 |
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David Harris
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56312cd0a6
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Clean up unused FPU signals
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2022-12-22 23:53:09 -08:00 |
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David Harris
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4d509f94ec
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FDIV merge
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2022-12-22 23:03:03 -08:00 |
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David Harris
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2d72bed1f4
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Removed unused signals in FPU and CSR
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2022-12-22 22:59:05 -08:00 |
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Ross Thompson
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98b824c4c4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-22 22:51:33 -06:00 |
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Ross Thompson
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2cc4d66ded
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Renamed IFU and LSU stalls.
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2022-12-22 21:56:33 -06:00 |
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Ross Thompson
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03021765a6
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The LSU is properly using FlushW rather than TrapM.
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2022-12-22 21:47:34 -06:00 |
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Ross Thompson
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3b791b768a
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Success we've replaced TrapM with FlushD in the IFU.
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2022-12-22 21:36:49 -06:00 |
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Ross Thompson
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e0e92952c3
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Partial cleanup for BP.
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2022-12-22 20:33:38 -06:00 |
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Ross Thompson
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206bc7daa6
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Closing in on icache flushed by FlushD rather than TrapM.
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2022-12-22 20:19:09 -06:00 |
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Ross Thompson
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b1475df5e1
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Wavefile updates.
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2022-12-22 19:45:02 -06:00 |
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Kip Macsai-Goren
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ffae1c5ee6
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added fs=00 to status fp enabled test
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2022-12-22 15:15:53 -08:00 |
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Kip Macsai-Goren
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a768d70093
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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Kip Macsai-Goren
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7aadf50f26
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updated trap handler alignemnts to 64 bytes in priv tests
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2022-12-22 14:23:04 -08:00 |
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Ross Thompson
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41fe876e7a
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First pass at resolving ifu flush on trap rather than FlushD.
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2022-12-22 15:53:06 -06:00 |
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David Harris
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d4bedca1bf
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Code cleanup
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2022-12-22 10:04:50 -08:00 |
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cturek
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ccbad67497
|
Added negative-result int diviison support in U and UM registers. 13 tests pass!
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2022-12-22 16:25:37 +00:00 |
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cturek
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1b7ed72ece
|
Moved swap from qslc to otfc
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2022-12-22 15:44:50 +00:00 |
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cturek
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3574bedb08
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-22 05:45:00 +00:00 |
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cturek
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80ca75e216
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Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc.
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2022-12-22 05:44:55 +00:00 |
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David Harris
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c42967f5c6
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XMerge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-21 20:39:38 -08:00 |
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Ross Thompson
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c8c73f47d2
|
CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.
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2022-12-21 22:13:05 -06:00 |
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cturek
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0b4d81bd4a
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worked out some bugs with int div cycles
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2022-12-22 02:22:01 +00:00 |
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cturek
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c3fdc0ab23
|
Renamed signals to E and M stages, forwarded preprocessed n to fsm
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2022-12-22 00:43:27 +00:00 |
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Ross Thompson
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84f8d9953f
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Updated cache fsm names to match book.
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2022-12-21 16:49:53 -06:00 |
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Ross Thompson
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d72cf65809
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-21 16:13:09 -06:00 |
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Ross Thompson
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e7a44d8975
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Changed GatedStallF to GatedStallD.
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2022-12-21 16:12:55 -06:00 |
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David Harris
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d0a3e939e3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-12-21 14:12:25 -08:00 |
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David Harris
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8bc753a291
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Added assertion about atomics needing caches
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2022-12-21 13:57:28 -08:00 |
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Ross Thompson
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e5f7e68d31
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2022-12-21 14:57:19 -06:00 |
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Ross Thompson
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b7224cc5ba
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Updated fpga constraints.
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2022-12-21 14:50:01 -06:00 |
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cturek
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0c30ecf86d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-21 20:41:38 +00:00 |
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David Harris
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6d46261350
|
comment cleanup
|
2022-12-21 12:39:09 -08:00 |
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David Harris
|
c7f3aae084
|
Only delegated bits of SIP are readable
|
2022-12-21 12:32:49 -08:00 |
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