32 Commits

Author	SHA1	Message	Date
Jacob Pease	b667581ffa	Refactored SPI peripheral based on SPI controller module. Works in tests/custom/spitest.	2024-10-29 17:50:36 -05:00
David Harris	1c1acc467e	Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0	2024-10-26 02:01:09 -07:00
Rose Thompson	a4cda877ef	Fixed bit position of SPI fifo receive and transmit flags.	2024-10-21 14:52:40 -05:00
Rose Thompson	32624bc6ee	Relocated a logic in a file to avoid a future merge conflict.	2024-09-05 12:50:09 -07:00
Rose Thompson	005ea52b72	Added missing signal declaration for SPI.	2024-09-05 12:20:06 -07:00
Rose Thompson	ac047a04fa	Fixed bug in SPI with the help of Naiche and Jacob. Have yet to test ... if SPI will now run correctly with div=0 (SYSTEMCLOCK/2), but the SPI flash card now correctly loads into the Linux OS and mount and is reading and writting without error.	2024-09-04 17:51:48 -07:00
naichewa	3b7661dfd5	SckDiv Zero bug fixes	2024-09-03 14:58:46 -07:00
Jacob Pease	938879c5a4	Update PREADY signal to not stall during transmission on reads to read only registers.	2024-08-21 12:39:01 -05:00
Jacob Pease	b7edffdfd4	Removed now inaccurate comments.	2024-08-20 16:38:15 -05:00
Jacob Pease	d8b75440b6	With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.	2024-08-20 16:24:37 -05:00
Jacob Pease	43b17b5058	Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose.	2024-08-20 14:40:50 -05:00
Jacob Pease	11a057b0b3	Updated wally source files for zsbl testing.	2024-08-02 15:33:57 -05:00
Jacob Pease	a506d76149	Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.	2024-07-22 12:36:39 -05:00
David Harris	cb563e8018	Clean up unused signals	2024-06-18 08:07:14 -07:00
David Harris	7509e856df	Removed asynchronous reset causing lint issue in peripherals	2024-06-18 05:49:12 -07:00
David Harris	0419b5484a	parameterized register names in peripherals	2024-04-21 07:43:01 -07:00
Kunlin Han	8c67a76912	Remove all #delay from non-testbench.	2024-03-13 10:31:40 -07:00
David Harris	d3ce683e06	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
naichewa	1ab7c926ea	Final Code Review	2023-11-14 13:44:59 -08:00
naichewa	5ce16dcb63	Cleanup	2023-11-09 16:52:55 -08:00
naichewa	3052a68d84	Remove old 2/4 bit logic, add comments, ... clean up unused signals	2023-11-09 16:48:11 -08:00
naichewa	b13b8feee4	updated to-do comments	2023-11-08 15:28:51 -08:00
naichewa	d67badfc60	fix hardware interlock, hold mode deassert	2023-11-08 15:20:51 -08:00
naichewa	a5837eb62c	fifo fixes and edge case testing	2023-11-07 17:59:46 -08:00
naichewa	29e42b21df	added test cases	2023-11-02 15:42:28 -07:00
naichewa	e3d8162279	harris code review 3	2023-11-01 10:14:15 -07:00
naichewa	9aa8a7af3e	comments, more test cases	2023-11-01 01:26:34 -07:00
naichewa	fefb5adb8f	code review harris	2023-10-31 12:27:41 -07:00
naichewa	2330f4ee63	hardware interlock	2023-10-30 17:00:20 -07:00
naichewa	4941fe1769	sync fifo passes	2023-10-16 22:57:02 -07:00
naichewa	aa5abfc8e8	always working after reg bit swizzle changes	2023-10-13 14:22:32 -07:00
naichewa	d5d4f9d044	transferred spi changes in ECA-authorized commit	2023-10-12 13:36:57 -07:00