mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
ac047a04fa
if SPI will now run correctly with div=0 (SYSTEMCLOCK/2), but the SPI flash card now correctly loads into the Linux OS and mount and is reading and writting without error.
469 lines
24 KiB
Systemverilog
469 lines
24 KiB
Systemverilog
///////////////////////////////////////////
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// spi_apb.sv
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//
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// Written: Naiche Whyte-Aguayo nwhyteaguayo@g.hmc.edu 11/16/2022
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//
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// Purpose: SPI peripheral
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//
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// SPI module is written to the specifications described in FU540-C000-v1.0. At the top level, it is consists of synchronous 8 byte transmit and recieve FIFOs connected to shift registers.
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// The FIFOs are connected to WALLY by an apb control register interface, which includes various control registers for modifying the SPI transmission along with registers for writing
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// to the transmit FIFO and reading from the receive FIFO. The transmissions themselves are then controlled by a finite state machine. The SPI module uses 4 tristate pins for SPI input/output,
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// along with a 4 bit Chip Select signal, a clock signal, and an interrupt signal to WALLY.
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// Current limitations: Flash read sequencer mode not implemented, dual and quad mode not supported
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module spi_apb import cvw::*; #(parameter cvw_t P) (
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input logic PCLK, PRESETn,
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input logic PSEL,
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input logic [7:0] PADDR,
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input logic [P.XLEN-1:0] PWDATA,
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input logic [P.XLEN/8-1:0] PSTRB,
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input logic PWRITE,
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input logic PENABLE,
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output logic PREADY,
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output logic [P.XLEN-1:0] PRDATA,
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output logic SPIOut,
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input logic SPIIn,
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output logic [3:0] SPICS,
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output logic SPIIntr,
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output logic SPICLK
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);
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// register map
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localparam SPI_SCKDIV = 8'h00;
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localparam SPI_SCKMODE = 8'h04;
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localparam SPI_CSID = 8'h10;
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localparam SPI_CSDEF = 8'h14;
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localparam SPI_CSMODE = 8'h18;
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localparam SPI_DELAY0 = 8'h28;
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localparam SPI_DELAY1 = 8'h2C;
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localparam SPI_FMT = 8'h40;
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localparam SPI_TXDATA = 8'h48;
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localparam SPI_RXDATA = 8'h4C;
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localparam SPI_TXMARK = 8'h50;
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localparam SPI_RXMARK = 8'h54;
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localparam SPI_IE = 8'h70;
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localparam SPI_IP = 8'h74;
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// receive shift register states
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typedef enum logic [1:0] {ReceiveShiftFullState, ReceiveShiftNotFullState, ReceiveShiftDelayState} rsrstatetype;
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// SPI control registers. Refer to SiFive FU540-C000 manual
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logic [11:0] SckDiv;
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logic [1:0] SckMode;
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logic [1:0] ChipSelectID;
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logic [3:0] ChipSelectDef;
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logic [1:0] ChipSelectMode;
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logic [15:0] Delay0, Delay1;
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logic [4:0] Format;
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logic [7:0] ReceiveData;
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logic [2:0] TransmitWatermark, ReceiveWatermark;
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logic [8:0] TransmitData;
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logic [1:0] InterruptEnable, InterruptPending;
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// Bus interface signals
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logic [7:0] Entry;
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logic Memwrite;
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logic [31:0] Din, Dout;
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logic TransmitInactive; // High when there is no transmission, used as hardware interlock signal
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// FIFO FSM signals
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// Watermark signals - TransmitReadMark = ip[0], ReceiveWriteMark = ip[1]
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logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark;
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logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty;
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logic TransmitFIFOWriteIncrement;
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logic ReceiveFiFoWriteInc;
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logic ReceiveFIFOReadIncrement;
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logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
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logic [7:0] TransmitFIFOReadData;
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/* verilator lint_off UNDRIVEN */
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logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel; // unused generic FIFO outputs
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/* verilator lint_off UNDRIVEN */
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logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
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rsrstatetype ReceiveState;
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// Transmission signals
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logic ZeroDiv; // High when SckDiv is 0
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logic [11:0] DivCounter; // Counter for sck
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logic SCLKenable; // Flip flop enable high every sclk edge
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// Delay signals
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logic [8:0] ImplicitDelay1; // Adds implicit delay to cs-sck delay counter based on phase
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logic [8:0] ImplicitDelay2; // Adds implicit delay to sck-cs delay counter based on phase
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logic [8:0] CS_SCKCount; // Counter for cs-sck delay
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logic [8:0] SCK_CSCount; // Counter for sck-cs delay
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logic [8:0] InterCSCount; // Counter for inter cs delay
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logic [8:0] InterXFRCount; // Counter for inter xfr delay
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logic ZeroDelayHoldMode; // High when ChipSelectMode is hold and Delay1[15:8] (InterXFR delay) is 0
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// Frame counting signals
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logic FirstFrame;
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logic [3:0] FrameCount; // Counter for number of frames in transmission
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logic ReceivePenultimateFrame; // High when penultimate frame in transmission has been reached
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// State fsm signals
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logic Active; // High when state is either Active1 or Active0 (during transmission)
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logic Active0; // High when state is Active0
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// Shift reg signals
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logic ShiftEdge; // Determines which edge of sck to shift from TransmitShiftReg
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logic [7:0] TransmitShiftReg; // Transmit shift register
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logic [7:0] ReceiveShiftReg; // Receive shift register
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logic SampleEdge; // Determines which edge of sck to sample from ReceiveShiftReg
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logic [7:0] TransmitDataEndian; // Reverses TransmitData from txFIFO if littleendian, since TransmitReg always shifts MSB
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logic TransmitShiftRegLoad; // Determines when to load TransmitShiftReg
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logic TransmitShiftRegLoadSingleCycle; // Version of TransmitShiftRegLoad which is only high for a single SCLK cycle to prevent double loads
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logic TransmitShiftRegLoadDelay; // TransmitShiftRegLoad delayed by an SCLK cycle, inverted and anded with TransmitShiftRegLoad to create a single cycle signal
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logic TransmitFIFOReadIncrement; // Increments Tx FIFO read ptr 1 cycle after Tx FIFO is read
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logic ReceiveShiftFull; // High when receive shift register is full
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logic TransmitShiftEmpty; // High when transmit shift register is empty
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logic ShiftIn; // Determines whether to shift from SPIIn or SPIOut (if SPI_LOOPBACK_TEST)
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logic [3:0] LeftShiftAmount; // Determines left shift amount to left-align data when little endian
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logic [7:0] ASR; // AlignedReceiveShiftReg
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logic ShiftEdgeSPICLK; // Changes ShiftEdge when SckDiv is 0
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// CS signals
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logic [3:0] ChipSelectAuto; // Assigns ChipSelect value to selected CS signal based on CS ID
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logic [3:0] ChipSelectInternal; // Defines what each ChipSelect signal should be based on transmission status and ChipSelectDef
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logic DelayMode; // Determines where to place implicit half cycle delay based on sck phase for CS assertion
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// Miscellaneous signals delayed/early by 1 PCLK cycle
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logic ReceiveShiftFullDelay; // Delays ReceiveShiftFull signal by 1 PCLK cycle
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logic ReceiveShiftFullDelayPCLK; // ReceiveShiftFull delayed by 1 PCLK cycle
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logic TransmitFIFOReadEmptyDelay;
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logic SCLKenableEarly; // SCLKenable 1 PCLK cycle early, needed for on time register changes when ChipSelectMode is hold and Delay1[15:8] (InterXFR delay) is 0
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// APB access
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assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
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assign Memwrite = PWRITE & PENABLE & PSEL; // Only write in access phase
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assign PREADY = Entry == SPI_TXDATA | Entry == SPI_RXDATA | Entry == SPI_IP | TransmitInactive; // Tie PREADY to transmission for hardware interlock
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// Account for subword read/write circuitry
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// -- Note SPI registers are 32 bits no matter what; access them with LW SW.
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assign Din = PWDATA[31:0];
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if (P.XLEN == 64) assign PRDATA = { Dout, Dout};
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else assign PRDATA = Dout;
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// Register access
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always_ff@(posedge PCLK)
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if (~PRESETn) begin
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SckDiv <= 12'd3;
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SckMode <= 2'b0;
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ChipSelectID <= 2'b0;
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ChipSelectDef <= 4'b1111;
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ChipSelectMode <= 2'b0;
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Delay0 <= {8'b1,8'b1};
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Delay1 <= {8'b0,8'b1};
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Format <= {5'b10000};
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TransmitData <= 9'b0;
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TransmitWatermark <= 3'b0;
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ReceiveWatermark <= 3'b0;
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InterruptEnable <= 2'b0;
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InterruptPending <= 2'b0;
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end else begin // writes
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/* verilator lint_off CASEINCOMPLETE */
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if (Memwrite & TransmitInactive)
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case(Entry) // flop to sample inputs
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SPI_SCKDIV: SckDiv <= Din[11:0];
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SPI_SCKMODE: SckMode <= Din[1:0];
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SPI_CSID: ChipSelectID <= Din[1:0];
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SPI_CSDEF: ChipSelectDef <= Din[3:0];
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SPI_CSMODE: ChipSelectMode <= Din[1:0];
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SPI_DELAY0: Delay0 <= {Din[23:16], Din[7:0]};
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SPI_DELAY1: Delay1 <= {Din[23:16], Din[7:0]};
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SPI_FMT: Format <= {Din[19:16], Din[2]};
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SPI_TXMARK: TransmitWatermark <= Din[2:0];
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SPI_RXMARK: ReceiveWatermark <= Din[2:0];
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SPI_IE: InterruptEnable <= Din[1:0];
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endcase
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if (Memwrite)
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case(Entry)
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SPI_TXDATA: if (~TransmitFIFOWriteFull) TransmitData[7:0] <= Din[7:0];
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endcase
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/* verilator lint_off CASEINCOMPLETE */
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// According to FU540 spec: Once interrupt is pending, it will remain set until number
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// of entries in tx/rx fifo is strictly more/less than tx/rxmark
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InterruptPending[0] <= TransmitReadMark;
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InterruptPending[1] <= RecieveWriteMark;
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case(Entry) // Flop to sample inputs
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SPI_SCKDIV: Dout <= {20'b0, SckDiv};
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SPI_SCKMODE: Dout <= {30'b0, SckMode};
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SPI_CSID: Dout <= {30'b0, ChipSelectID};
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SPI_CSDEF: Dout <= {28'b0, ChipSelectDef};
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SPI_CSMODE: Dout <= {30'b0, ChipSelectMode};
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SPI_DELAY0: Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]};
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SPI_DELAY1: Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]};
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SPI_FMT: Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0};
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SPI_TXDATA: Dout <= {23'b0, TransmitFIFOWriteFull, 8'b0};
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SPI_RXDATA: Dout <= {23'b0, ReceiveFIFOReadEmpty, ReceiveData[7:0]};
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SPI_TXMARK: Dout <= {29'b0, TransmitWatermark};
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SPI_RXMARK: Dout <= {29'b0, ReceiveWatermark};
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SPI_IE: Dout <= {30'b0, InterruptEnable};
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SPI_IP: Dout <= {30'b0, InterruptPending};
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default: Dout <= 32'b0;
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endcase
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end
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// SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
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// Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv
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// Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
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// When SckDiv is 0, count doesn't work and SCLKenable is simply PCLK
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assign ZeroDiv = ~|(SckDiv[10:0]);
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assign SCLKenable = ZeroDiv ? PCLK : (DivCounter == SckDiv);
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assign SCLKenableEarly = ((DivCounter + 12'b1) == SckDiv);
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always_ff @(posedge PCLK)
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if (~PRESETn) DivCounter <= '0;
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else if (SCLKenable) DivCounter <= 12'b0;
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else DivCounter <= DivCounter + 12'b1;
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// Asserts when transmission is one frame before complete
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assign ReceivePenultimateFrame = ((FrameCount + 4'b0001) == Format[4:1]);
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assign FirstFrame = (FrameCount == 4'b0);
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// Computing delays
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// When sckmode.pha = 0, an extra half-period delay is implicit in the cs-sck delay, and vice-versa for sck-cs
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assign ImplicitDelay1 = SckMode[0] ? 9'b0 : 9'b1;
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assign ImplicitDelay2 = SckMode[0] ? 9'b1 : 9'b0;
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// Calculate when tx/rx shift registers are full/empty
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// Transmit Shift FSM
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always_ff @(posedge PCLK)
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if (~PRESETn) TransmitShiftEmpty <= 1'b1;
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else if (TransmitShiftEmpty) begin
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if (TransmitFIFOReadEmpty | (~TransmitFIFOReadEmpty & (ReceivePenultimateFrame & Active0))) TransmitShiftEmpty <= 1'b1;
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else if (~TransmitFIFOReadEmpty) TransmitShiftEmpty <= 1'b0;
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end else begin
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if (ReceivePenultimateFrame & Active0) TransmitShiftEmpty <= 1'b1;
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else TransmitShiftEmpty <= 1'b0;
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end
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// Receive Shift FSM
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always_ff @(posedge PCLK)
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if (~PRESETn) ReceiveState <= ReceiveShiftNotFullState;
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else if (SCLKenable) begin
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case (ReceiveState)
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ReceiveShiftFullState: ReceiveState <= ReceiveShiftNotFullState;
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ReceiveShiftNotFullState: if (ReceivePenultimateFrame & (SampleEdge)) ReceiveState <= ReceiveShiftDelayState;
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else ReceiveState <= ReceiveShiftNotFullState;
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ReceiveShiftDelayState: ReceiveState <= ReceiveShiftFullState;
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endcase
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end
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assign ReceiveShiftFull = SckMode[0] ? (ReceiveState == ReceiveShiftFullState) : (ReceiveState == ReceiveShiftDelayState);
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// Calculate tx/rx fifo write and recieve increment signals
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always_ff @(posedge PCLK)
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if (~PRESETn) TransmitFIFOWriteIncrement <= 1'b0;
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else TransmitFIFOWriteIncrement <= (Memwrite & (Entry == SPI_TXDATA) & ~TransmitFIFOWriteFull);
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always_ff @(posedge PCLK)
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if (~PRESETn) ReceiveFIFOReadIncrement <= 1'b0;
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else ReceiveFIFOReadIncrement <= ((Entry == SPI_RXDATA) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
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assign TransmitShiftRegLoad = ~TransmitShiftEmpty & ~Active | (((ChipSelectMode == 2'b10) & ~|(Delay1[15:8])) & ((ReceiveShiftFullDelay | ReceiveShiftFull) & ~SampleEdge & ~TransmitFIFOReadEmpty));
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always_ff @(posedge PCLK)
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if (~PRESETn) TransmitShiftRegLoadDelay <=0;
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else if (SCLKenable) TransmitShiftRegLoadDelay <= TransmitShiftRegLoad;
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assign TransmitShiftRegLoadSingleCycle = TransmitShiftRegLoad & ~TransmitShiftRegLoadDelay;
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always_ff @(posedge PCLK)
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if (~PRESETn) TransmitFIFOReadIncrement <= 0;
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else if (SCLKenable) TransmitFIFOReadIncrement <= TransmitShiftRegLoadSingleCycle;
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// Tx/Rx FIFOs
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spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitFIFOReadIncrement, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
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TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark);
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spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveFiFoWriteInc, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel,
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ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark);
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always_ff @(posedge PCLK)
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if (~PRESETn) TransmitFIFOReadEmptyDelay <= 1'b1;
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else if (SCLKenable) TransmitFIFOReadEmptyDelay <= TransmitFIFOReadEmpty;
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always_ff @(posedge PCLK)
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if (~PRESETn) ReceiveShiftFullDelay <= 1'b0;
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else if (SCLKenable) ReceiveShiftFullDelay <= ReceiveShiftFull;
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assign ReceiveFiFoTakingData = ReceiveFiFoWriteInc & ~ReceiveFIFOWriteFull;
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always_ff @(posedge PCLK)
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if (~PRESETn) ReceiveFiFoWriteInc <= 1'b0;
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else if (SCLKenable & ReceiveShiftFull) ReceiveFiFoWriteInc <= 1'b1;
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else if (SCLKenable & ReceiveFiFoTakingData) ReceiveFiFoWriteInc <= 1'b0;
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always_ff @(posedge PCLK)
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if (~PRESETn) ReceiveShiftFullDelayPCLK <= 1'b0;
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else if (SCLKenableEarly) ReceiveShiftFullDelayPCLK <= ReceiveShiftFull;
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// Main FSM which controls SPI transmission
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typedef enum logic [2:0] {CS_INACTIVE, DELAY_0, ACTIVE_0, ACTIVE_1, DELAY_1,INTER_CS, INTER_XFR} statetype;
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statetype state;
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always_ff @(posedge PCLK)
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if (~PRESETn) begin
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state <= CS_INACTIVE;
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FrameCount <= 4'b0;
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SPICLK <= SckMode[1];
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end else if (SCLKenable) begin
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/* verilator lint_off CASEINCOMPLETE */
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case (state)
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CS_INACTIVE: begin
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CS_SCKCount <= 9'b1;
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SCK_CSCount <= 9'b10;
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FrameCount <= 4'b0;
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InterCSCount <= 9'b10;
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InterXFRCount <= 9'b1;
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if ((~TransmitFIFOReadEmpty | ~TransmitShiftEmpty) & ((|(Delay0[7:0])) | ~SckMode[0])) state <= DELAY_0;
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else if ((~TransmitFIFOReadEmpty | ~TransmitShiftEmpty)) begin
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state <= ACTIVE_0;
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SPICLK <= ~SckMode[1];
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end else SPICLK <= SckMode[1];
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end
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DELAY_0: begin
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CS_SCKCount <= CS_SCKCount + 9'b1;
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if (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1)) begin
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state <= ACTIVE_0;
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SPICLK <= ~SckMode[1];
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end
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end
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ACTIVE_0: begin
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FrameCount <= FrameCount + 4'b1;
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SPICLK <= SckMode[1];
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state <= ACTIVE_1;
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end
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ACTIVE_1: begin
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InterXFRCount <= 9'b1;
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if (FrameCount < Format[4:1]) begin
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state <= ACTIVE_0;
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SPICLK <= ~SckMode[1];
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end
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else if ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty)) begin
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state <= ACTIVE_0;
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SPICLK <= ~SckMode[1];
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CS_SCKCount <= 9'b1;
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SCK_CSCount <= 9'b10;
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FrameCount <= 4'b0;
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InterCSCount <= 9'b10;
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end
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else if (ChipSelectMode[1:0] == 2'b10) state <= INTER_XFR;
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else if (~|(Delay0[15:8]) & (~SckMode[0])) state <= INTER_CS;
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else state <= DELAY_1;
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end
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DELAY_1: begin
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SCK_CSCount <= SCK_CSCount + 9'b1;
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if (SCK_CSCount >= (({Delay0[15:8], 1'b0}) + ImplicitDelay2)) state <= INTER_CS;
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end
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INTER_CS: begin
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InterCSCount <= InterCSCount + 9'b1;
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SPICLK <= SckMode[1];
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if (InterCSCount >= ({Delay1[7:0],1'b0})) state <= CS_INACTIVE;
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end
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INTER_XFR: begin
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CS_SCKCount <= 9'b1;
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SCK_CSCount <= 9'b10;
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FrameCount <= 4'b0;
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InterCSCount <= 9'b10;
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InterXFRCount <= InterXFRCount + 9'b1;
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if ((InterXFRCount >= ({Delay1[15:8], 1'b0})) & (~TransmitFIFOReadEmptyDelay | ~TransmitShiftEmpty)) begin
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state <= ACTIVE_0;
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SPICLK <= ~SckMode[1];
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end else if (~|ChipSelectMode[1:0]) state <= CS_INACTIVE;
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else SPICLK <= SckMode[1];
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end
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endcase
|
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/* verilator lint_off CASEINCOMPLETE */
|
|
end
|
|
|
|
|
|
|
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assign DelayMode = SckMode[0] ? (state == DELAY_1) : (state == ACTIVE_1 & ReceiveShiftFull);
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assign ChipSelectInternal = (state == CS_INACTIVE | state == INTER_CS | DelayMode & ~|(Delay0[15:8])) ? ChipSelectDef : ~ChipSelectDef;
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assign Active = (state == ACTIVE_0 | state == ACTIVE_1);
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assign SampleEdge = SckMode[0] ? (state == ACTIVE_1) : (state == ACTIVE_0);
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assign ZeroDelayHoldMode = ((ChipSelectMode == 2'b10) & (~|(Delay1[7:4])));
|
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assign TransmitInactive = ((state == INTER_CS) | (state == CS_INACTIVE) | (state == INTER_XFR) | (ReceiveShiftFullDelayPCLK & ZeroDelayHoldMode) | ((state == ACTIVE_1) & ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty) & (FrameCount == Format[4:1]))));
|
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assign Active0 = (state == ACTIVE_0);
|
|
assign ShiftEdgeSPICLK = ZeroDiv ? ~SPICLK : SPICLK;
|
|
|
|
// Signal tracks which edge of sck to shift data
|
|
always_comb
|
|
case(SckMode[1:0])
|
|
2'b00: ShiftEdge = ShiftEdgeSPICLK & SCLKenable;
|
|
2'b01: ShiftEdge = (~ShiftEdgeSPICLK & ~FirstFrame & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
|
|
2'b10: ShiftEdge = ~ShiftEdgeSPICLK & SCLKenable;
|
|
2'b11: ShiftEdge = (ShiftEdgeSPICLK & ~FirstFrame & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
|
|
default: ShiftEdge = ShiftEdgeSPICLK & SCLKenable;
|
|
endcase
|
|
|
|
// Transmit shift register
|
|
assign TransmitDataEndian = Format[0] ? {TransmitFIFOReadData[0], TransmitFIFOReadData[1], TransmitFIFOReadData[2], TransmitFIFOReadData[3], TransmitFIFOReadData[4], TransmitFIFOReadData[5], TransmitFIFOReadData[6], TransmitFIFOReadData[7]} : TransmitFIFOReadData[7:0];
|
|
always_ff @(posedge PCLK)
|
|
if(~PRESETn) TransmitShiftReg <= 8'b0;
|
|
else if (TransmitShiftRegLoadSingleCycle) TransmitShiftReg <= TransmitDataEndian;
|
|
else if (ShiftEdge & Active) TransmitShiftReg <= {TransmitShiftReg[6:0], TransmitShiftReg[0]};
|
|
|
|
assign SPIOut = TransmitShiftReg[7];
|
|
|
|
// If in loopback mode, receive shift register is connected directly to module's output pins. Else, connected to SPIIn
|
|
// There are no setup/hold time issues because transmit shift register and receive shift register always shift/sample on opposite edges
|
|
assign ShiftIn = P.SPI_LOOPBACK_TEST ? SPIOut : SPIIn;
|
|
|
|
// Receive shift register
|
|
always_ff @(posedge PCLK)
|
|
if(~PRESETn) ReceiveShiftReg <= 8'b0;
|
|
else if (SampleEdge & SCLKenable) begin
|
|
if (~Active) ReceiveShiftReg <= 8'b0;
|
|
else ReceiveShiftReg <= {ReceiveShiftReg[6:0], ShiftIn};
|
|
end
|
|
|
|
// Aligns received data and reverses if little-endian
|
|
assign LeftShiftAmount = 4'h8 - Format[4:1];
|
|
assign ASR = ReceiveShiftReg << LeftShiftAmount[2:0];
|
|
assign ReceiveShiftRegEndian = Format[0] ? {ASR[0], ASR[1], ASR[2], ASR[3], ASR[4], ASR[5], ASR[6], ASR[7]} : ASR[7:0];
|
|
|
|
// Interrupt logic: raise interrupt if any enabled interrupts are pending
|
|
assign SPIIntr = |(InterruptPending & InterruptEnable);
|
|
|
|
// Chip select logic
|
|
always_comb
|
|
case(ChipSelectID[1:0])
|
|
2'b00: ChipSelectAuto = {ChipSelectDef[3], ChipSelectDef[2], ChipSelectDef[1], ChipSelectInternal[0]};
|
|
2'b01: ChipSelectAuto = {ChipSelectDef[3],ChipSelectDef[2], ChipSelectInternal[1], ChipSelectDef[0]};
|
|
2'b10: ChipSelectAuto = {ChipSelectDef[3],ChipSelectInternal[2], ChipSelectDef[1], ChipSelectDef[0]};
|
|
2'b11: ChipSelectAuto = {ChipSelectInternal[3],ChipSelectDef[2], ChipSelectDef[1], ChipSelectDef[0]};
|
|
endcase
|
|
|
|
assign SPICS = ChipSelectMode[0] ? ChipSelectDef : ChipSelectAuto;
|
|
endmodule
|