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321 Commits

Author SHA1 Message Date
Kip Macsai-Goren
ba3bfdf68b Manual attempt to merge with upstream changes 2023-02-22 19:42:30 -08:00
Kip Macsai-Goren
0339dc5e78 added extra commands to make dut run work with spike for bit manip tests 2023-02-21 15:26:47 -08:00
Kip Macsai-Goren
d668c563f4 Merge remote-tracking branch 'upstream/main' into main 2023-02-21 14:48:41 -08:00
David Harris
99a1683f8e Debug test case updates 2023-02-21 09:33:36 -08:00
Kip Macsai-Goren
65a5b86dd8 Merge remote-tracking branch 'upstream/main' into main 2023-02-19 16:37:18 -08:00
David Harris
f0c0111ab0 Renamed section 12.3 to 8.3 in MMU test definitions 2023-02-19 05:46:46 -08:00
Kip Macsai-Goren
9c3aa55349 merge upstream synth changes 2023-02-18 14:35:19 -08:00
Kip Macsai-Goren
ea38e05773 fixed makefile for 32 bit arch tests, restored original make for all others 2023-02-17 09:57:56 -08:00
Kip Macsai-Goren
7344f3ef30 Modified arch64 tests to remove floating point and double tests from hanging make 2023-02-17 09:51:55 -08:00
David Harris
2b80004db4 Debug test case update 2023-02-15 06:42:38 -08:00
Kevin Kim
4fed8d9196 added critical rsync command to python script and builds I-ext tests 
-rsync copies the stuff from riscof_work to work/riscv-arch-test
-
 2023-02-14 10:40:29 -08:00
Kevin Kim
5fed4c2c87 updated python script to generate bash file 2023-02-11 11:08:11 -08:00
Kevin Kim
7e4fc40dc7 changed python file to use WALLY env variable 2023-02-11 00:30:56 +00:00
Kip Macsai-Goren
76593cb282 Added necessary files to make bit make and run bit manipulation tests as part of regression 2023-02-10 10:35:19 -08:00
David Harris
9a6d7bb16d Added RVTEST_CASE to testgen header 2023-02-09 18:25:24 -08:00
David Harris
8fb513ad35 Moved test generators 2023-02-09 18:24:48 -08:00
David Harris
edbf962b5f Test gen header 2023-02-09 18:14:26 -08:00
David Harris
44fef2f2a1 debug simulating, produing discrepancy 2023-02-06 16:47:56 -08:00
David Harris
4c219de13d Fixed floating point crash in debug.S 2023-02-06 15:38:57 -08:00
David Harris
5256d3a625 More progress on debug.S, but it crashes in Spike 2023-02-04 09:59:22 -08:00
David Harris
43668a3fc5 Developing debug test 2023-02-04 08:31:47 -08:00
David Harris
2c69adc5f7 Started making debug testcase 2023-02-04 08:18:55 -08:00
David Harris
80f42a8638 Renamed regression to sim 2023-02-02 14:48:23 -08:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00
David Harris
4883351bd2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-28 18:18:53 -08:00
Kip Macsai-Goren
ee1bcf62ee Fixed regression test dependance on bp status by adding handling of UART tx empty interrupts. 2023-01-28 17:29:35 -08:00
David Harris
d8f0e3dd70 Modified testgen to not produce reference outputs 2023-01-27 07:25:40 -08:00
David Harris
cea89f27cf Removed unused WALLY test references 2023-01-27 07:25:04 -08:00
David Harris
2af94bf283 Removed unused reference files 2023-01-27 07:21:55 -08:00
David Harris
37ba3d0fcd Removed f tests from rv32e 2023-01-27 06:15:20 -08:00
David Harris
7fbbed7927 Update riscof makefile to use rv32gc config 2023-01-27 05:57:58 -08:00
David Harris
b81b5781e1 Renamed spike_rv32imc_isa.yaml to rv32gc to reflect cases tested 2023-01-27 05:56:49 -08:00
David Harris
7d8a0d9615 Refactored setup QUESTA and SNPS paths, and removed troublesome bit manipulation test cases 2023-01-23 05:00:11 -08:00
David Harris
b173112f86 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
Ross Thompson
97feea2f48 Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
Ross Thompson
a35fb3addd core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
Ross Thompson
f8c656f1e0 Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
Kip Macsai-Goren
964084f0b3 added fs=00 to status fp enabled test 2022-12-22 15:15:53 -08:00
Kip Macsai-Goren
d25d699800 Added status.tvm bit test that passes make and regression 2022-12-22 14:43:22 -08:00
Kip Macsai-Goren
a37bde7452 updated trap handler alignemnts to 64 bytes in priv tests 2022-12-22 14:23:04 -08:00
David Harris
ca949f2110 Only delegated bits of SIP are readable 2022-12-21 12:32:49 -08:00
Ross Thompson
f6393d1288 Waiting on fix for wally64periph uart test. 
would like to remove vectored interrupt adder.
 2022-12-21 13:16:09 -06:00
Ross Thompson
c41d58bd29 Vectored interrupts now require 64 byte alignment. 
Eliminates adder.
 2022-12-21 12:05:49 -06:00
David Harris
00ff823d84 Restored rv32d arch test after new push 2022-12-20 10:56:33 -08:00
Ross Thompson
c3b77926d5 I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
Ross Thompson
e8c1d14abb Have a basic cache test to fill all ways and sets. 2022-12-18 17:20:30 -06:00
Ross Thompson
7a352edf13 Attempted to make a cache test. 2022-12-18 17:15:08 -06:00
Ross Thompson
9d1cb9337e Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
David Harris
643a2e7cf9 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
Kip Macsai-Goren
55627f40e2 added passing GPIO test to 64 bit tests 2022-12-05 21:31:00 -08:00