Jordan Carlin
4c0e4846ea
More debugging
2024-10-18 16:03:56 -07:00
Jordan Carlin
f15ef57cb9
Debugging
2024-10-18 16:03:56 -07:00
Jordan Carlin
638591e1dd
Update coverage test files. Assembler is picky and only accepts # comments and needs newlines
2024-10-18 16:03:55 -07:00
Jordan Carlin
4a81327b04
Use assembler instead of compiler for coverage tests
2024-10-18 16:03:55 -07:00
Jordan Carlin
1e204f3c12
Update testfloat README formatting
2024-10-17 15:21:37 -07:00
David Harris
aaa2edac18
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-10-16 13:26:51 -07:00
Rose Thompson
8fb1673ab3
Updated email address authorship for my files.
2024-10-15 10:27:53 -05:00
David Harris
9a76af809a
Documented ecall services in WALLY-init-lib
2024-10-14 15:28:28 -07:00
Rose Thompson
f208b11b51
Update hptwAccessFault to generate additional hptw access faults
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during ifu fetches.
2024-10-14 16:51:46 -05:00
Rose Thompson
d8fe68b912
Merge pull request #1011 from davidharrishmc/dev
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Fixed bug causing Issue 1010 and made some changes to Wally privileged fields to match ImperasDV
2024-10-14 11:10:21 -05:00
David Harris
5e550554b5
Fixed bug in WALLY-init-lib label for RV32
2024-10-14 08:58:37 -07:00
Jordan Carlin
e7b9369f7f
Merge pull request #1008 from davidharrishmc/dev
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Fix mcountinhibit bit 1 that should be hardwired to 0
2024-10-13 22:44:35 -07:00
David Harris
669ee6ca12
WALLY-init-lib improvements to support functional coverage
2024-10-13 20:59:41 -07:00
Rose Thompson
2ef7005ea6
Fixed name of test and added to tests.vh
2024-10-13 15:29:27 -05:00
Rose Thompson
37d3db916b
Resolved the HPTW's not taking the PBMT fault on the right cycle by
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having the fsm branch to fault on any cycle a HPTWFaultM occurs. This
of course changes the figure in the book but it really relevant to
PBMT. This appeared to work because the HPTW happened to also generate
an access fault at the end of the walk and the logic produced both
faults. I wrote new test which confirms just the one is generated.
2024-10-11 15:31:20 -05:00
Rose Thompson
971a208956
Removed cacheSimTest. Unknown what it does or how it is used. Is not
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referenced anywhere.
2024-10-02 16:18:11 -05:00
Rose Thompson
ebdef07301
Moved the simple branch predictor custom test into the gshare.S
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coverage test.
2024-10-02 16:11:54 -05:00
Rose Thompson
a56ef9e267
Removed unused benchmarks.
2024-10-02 15:59:33 -05:00
Rose Thompson
bf31182b91
Moved tests/custom/debug.S to tests/coverage/floatmisc.S
2024-10-02 15:56:10 -05:00
Rose Thompson
1c1ac94bf1
Removed old used tests from the custom directory.
2024-10-02 15:07:52 -05:00
Rose Thompson
1e2a9e3b18
Added test to check for AMO access fault.
2024-10-02 14:17:37 -05:00
Jordan Carlin
9363379b55
Combine floating point test documentation
2024-10-01 12:44:47 -07:00
Rose Thompson
93272747b3
New test to check for hptw access faults.
2024-10-01 10:38:26 -05:00
Rose Thompson
0f5976476d
More corrections to tlbMisaligned comment header.
2024-09-30 17:25:37 -05:00
Rose Thompson
047922365a
Update header with correct author and description.
2024-09-30 17:19:16 -05:00
Rose Thompson
4fc7516694
Created test to show TLB misses supress misaligned faults. Test first
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checks cached accesses which should not cause misaligned faults and
then uses PBMT to disable cachablity.
2024-09-30 16:39:59 -05:00
Jordan Carlin
022b98a64b
Update all iterative makes to use
2024-09-29 23:14:19 -07:00
Jordan Carlin
90342915af
Cleanup makefile printing
2024-09-29 17:24:24 -07:00
Jordan Carlin
4092f27b07
Fix bit-width of memfile for rv64 riscv-arch-test floating point tests
2024-09-29 17:24:08 -07:00
Jordan Carlin
8a58f9556e
Merge branch 'main' of https://github.com/openhwgroup/cvw into arch-test-update
2024-09-29 17:16:05 -07:00
Jordan Carlin
68b854fc20
Finish updating riscof and sim Makefiles to allow targets to run in parallel
2024-09-29 14:05:28 -07:00
Jordan Carlin
8cb0c08e68
more wally-riscv-arch-test cleanup
2024-09-29 10:28:31 -07:00
Jordan Carlin
766b0a83d7
Remove wally32d tests since they are covered elsewhere now
2024-09-29 10:27:20 -07:00
Jordan Carlin
330eda243c
Remove wally32i and wally64i tests since they are covered elsewhere now
2024-09-29 10:26:08 -07:00
Jordan Carlin
4c5f397afd
Remove old testgen scripts
2024-09-29 10:22:12 -07:00
Jordan Carlin
4cacc6b80c
More testfloat makefile cleanup
2024-09-29 01:05:38 -07:00
Jordan Carlin
478ed242ad
More testfloat gen updates to switch to just riscv vectors
2024-09-29 00:32:18 -07:00
Jordan Carlin
495d1c7145
Only generate RISCV version of softfloat
2024-09-28 21:43:41 -07:00
Jordan Carlin
14b630a403
More testfloat fixups
2024-09-28 20:56:58 -07:00
Jordan Carlin
0c2ce32c56
Update fp Makefile to generate softfloat
2024-09-28 20:23:27 -07:00
Jordan Carlin
bf0c7fba95
Update fp Makefile to generate softfloat
2024-09-28 20:20:06 -07:00
Jordan Carlin
0bfd0dc32d
Add license header to new floating point Makefiles
2024-09-20 16:43:36 -07:00
Jordan Carlin
d7edeef79a
Update top level floating point test Makefile to build all vectors and testfloat binaries
2024-09-20 16:28:05 -07:00
Jordan Carlin
766678d076
Add clean target to vector makefile
2024-09-20 16:22:25 -07:00
Jordan Carlin
aa1a86c70e
More testfloat Makefile refactoring and fix using the wrong softfloat
2024-09-19 15:34:16 -07:00
Jordan Carlin
90cf61401e
Fix testfloat Makefile
2024-09-19 13:39:24 -07:00
Jordan Carlin
cc92cb125f
Makefile for all fp testvectors
2024-09-19 13:38:35 -07:00
Jordan Carlin
7071d15341
Initial attempt at two separate version of testfloat for riscv and ieee
2024-09-18 17:37:29 -07:00
Jordan Carlin
c13c57b5a6
Refactor floating point testvector Makefile to split up RISCV and IEEE due to Make issues
2024-09-18 17:37:02 -07:00
Jordan Carlin
cb944e0f92
Remove old testfloat and replace references
2024-09-15 01:03:03 -07:00
Jordan Carlin
7e41961dd1
Remove old softfloat and replace references
2024-09-15 00:34:18 -07:00
Jordan Carlin
f7b93ac700
More simplification of fp testvector makefile
2024-09-14 20:59:00 -07:00
Jordan Carlin
d2ef362761
Fix testfloat cvtint generation
2024-09-14 20:16:28 -07:00
Jordan Carlin
ec8302d597
Split up cvtint and cvtfp tests
2024-09-14 20:11:09 -07:00
David Harris
6e0b0487dd
Recreated coverage changes
2024-09-05 16:32:45 -07:00
David Harris
712274af3d
Removed covergen makefile
2024-09-05 16:29:07 -07:00
David Harris
941d662b59
Removed covergen
2024-09-05 16:28:48 -07:00
naichewa
58be9e0556
Merge branch 'spi_debug'
2024-09-03 15:00:59 -07:00
naichewa
3b7661dfd5
SckDiv Zero bug fixes
2024-09-03 14:58:46 -07:00
David Harris
ff9f0fa140
Updated riscv-isac dependencies for security
2024-09-03 03:46:44 -07:00
Jacob Pease
3b91977227
Added start.s to spitest directory.
2024-08-28 04:10:24 -05:00
Jacob Pease
44ece7cb96
Added CVW header to spitest files.
2024-08-27 14:28:49 -05:00
Jacob Pease
b7a74307c5
Committing the custom test spitest.
2024-08-27 14:19:56 -05:00
Rose Thompson
6be30369f1
Merge branch 'main' of github.com:openhwgroup/cvw
2024-08-21 11:02:23 -07:00
Rose Thompson
faffecf891
Merge branch 'main' of github.com:openhwgroup/cvw
2024-08-21 11:02:17 -07:00
Rose Thompson
01b623b8c4
Merge branch 'main' of github.com:openhwgroup/cvw
2024-08-21 11:02:08 -07:00
Rose Thompson
f603d21826
Updated my name in multiple locations.
2024-08-21 10:50:39 -07:00
Huda-10xe
ca21b865b3
Adding regression commands to Makefile
2024-08-21 15:45:23 +05:00
Jacob Pease
baad4e0fd2
With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
2024-08-20 16:24:37 -05:00
David Harris
f4871c14f7
Merge pull request #918 from jordancarlin/fp_tests_make
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Testfloat vector generation refactoring + root Makefile cleanup
2024-08-17 04:32:45 -07:00
David Harris
ef7028154c
Merge pull request #873 from Shreesh-Kulkarni/main
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Modified riscv-isacov and riscv-ctg files to support some missing quad instructions.
2024-08-16 11:10:35 -07:00
Jordan Carlin
d6110c3d0b
Set riscof jobs based on number of cores
2024-08-15 19:02:48 -07:00
Jordan Carlin
3b85f92695
Testfloat vector generation refactoring
2024-08-15 18:53:26 -07:00
Jordan Carlin
6d77398c95
Update linker scripts to avoid hardcoded /opt/riscv
2024-08-09 20:15:28 -07:00
Jordan Carlin
357175f1c8
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-08-07 20:22:55 -07:00
Huda-10xe
2405b6c1e2
Adding RVVI Functional Coverage Support
2024-08-07 14:31:16 +05:00
Jordan Carlin
2f1a101735
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-25 21:21:57 -07:00
David Harris
b7fb786749
Increased covergen.py functional coverage to 87.6%
2024-07-23 04:38:13 -07:00
David Harris
a9fd6e6cfb
Added more RV64I coverage generation
2024-07-22 08:52:19 -07:00
David Harris
6ca7845c93
Fixed hazard and rd_maxval coverage generation
2024-07-21 19:46:30 -07:00
Shreesh-Kulkarni
82b42a5faf
Modified riscv-isacov and riscv-ctg files to support some missing quad instructions. Needs debugging.
2024-07-06 08:57:32 -07:00
Jordan Carlin
e6e070f4e4
Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)
2024-07-03 20:42:55 -07:00
Jordan Carlin
2b4f12916e
Merge pull request #858 from davidharrishmc/dev
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Regression Improvements
2024-07-01 20:04:31 -07:00
James Stine
f660779ba9
Fix for Q causing it to error out - commented out line for ISA and reset-val so can be put back
2024-06-28 12:17:15 -05:00
David Harris
8fe2052b1f
Fix derived configuration with new derivgen script
2024-06-26 16:09:59 -07:00
David Harris
21e5fa3103
Merge pull request #854 from Shreesh-Kulkarni/main
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Files for Quad Precision Testing Support for Wally
2024-06-26 11:41:26 -07:00
Shreesh-Kulkarni
93fb0f2a84
Files for Quad Precision Testing Support for Wally
2024-06-26 11:36:04 -07:00
David Harris
0fcc7878dc
Updated march lists
2024-06-25 21:54:58 -07:00
David Harris
d8d94eeafa
Merge pull request #808 from jordancarlin/main
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Update riscv-arch-test
2024-06-20 08:43:41 -07:00
Ross Thompson
9e93f21990
Updated covergen to not include stores as they are incomplete.
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Modified makefile riscv-dv to not simulation only generate tests.
2024-06-19 15:13:49 -07:00
Jordan Carlin
d58b454a8b
Finish switching Zfa to use riscv-arch-test
2024-06-18 23:31:37 -07:00
Jordan Carlin
6f79dca9c4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-27 12:29:24 -07:00
Quswar Abid
997b5901cc
sb types are all passing, loaditypes are not!
2024-05-27 04:27:50 -07:00
Quswar Abid
1bf9b13953
added some sb types
2024-05-27 03:58:38 -07:00
Quswar Abid
29d7cd5663
unwanted comments
2024-05-27 03:58:38 -07:00
Quswar Abid
8edc4057ed
compilable tests generating for loaditypes[lb, lh, lw, ld, lbu, lhu, lwu]
2024-05-27 03:58:38 -07:00
Jordan Carlin
dcafe4793e
Add froundnx and fround.d tests
2024-05-24 15:16:35 -07:00
Jordan Carlin
f410bbb79e
Use Zfa tests from riscv-arch-test instead of wally-riscv-arch-test
2024-05-21 00:04:27 -07:00
Rose Thompson
e295454948
Merge pull request #798 from jordancarlin/newConfig
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Update config to derive MISA from macros and update MISA bits based on the spec
2024-05-15 10:28:44 -05:00
Jordan Carlin
1065b8977a
Fix Q_SUPPORTED on derived configs
2024-05-14 11:49:54 -07:00
