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Merge pull request #873 from Shreesh-Kulkarni/main

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Modified riscv-isacov and riscv-ctg files to support some missing quad instructions.
This commit is contained in:
David Harris 2024-08-16 11:10:35 -07:00 committed by GitHub
commit ef7028154c
6 changed files with 42 additions and 17 deletions
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6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/generator.py
View File

@ -55,7 +55,7 @@ def toint(x: str):
return int(x)
def get_rm(opcode):
insns = ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','fmin','fmax',
insns = ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','flq','fsq','fmin','fmax',
'fcvt.d.s', 'fcvt.d.w','fcvt.d.wu']
insns += ['fminm', 'fmaxm']
if any([x in opcode for x in insns]):
@ -242,7 +242,7 @@ class Generator():
is_nan_box = False
is_fext = any(['F' in x or 'D' in x for x in opnode['isa']])
is_fext = any(['F' in x or 'D' in x or 'Q' in x for x in opnode['isa']])
if is_fext:
if fl>ifl:
@ -260,7 +260,7 @@ class Generator():
self.is_fext = is_fext
self.is_nan_box = is_nan_box
if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd"]:
if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd","flq","fsq"]:
self.val_vars = self.val_vars + ['ea_align']
self.template = opnode['template']
self.opnode = opnode

19
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/riscv_isac/InstructionObject.py
View File

@ -2,7 +2,7 @@ import struct
instrs_sig_mutable = ['auipc','jal','jalr']
instrs_sig_update = ['sh','sb','sw','sd','c.sw','c.sd','c.swsp','c.sdsp','fsw','fsd',\
'c.fsw','c.fsd','c.fswsp','c.fsdsp']
'fsq','c.fsw','c.fsd','c.fswsp','c.fsdsp']
instrs_no_reg_tracking = ['beq','bne','blt','bge','bltu','bgeu','fence','c.j','c.jal','c.jalr',\
'c.jr','c.beqz','c.bnez', 'c.ebreak'] + instrs_sig_update
instrs_fcsr_affected = ['fmadd.s','fmsub.s','fnmsub.s','fnmadd.s','fadd.s','fsub.s','fmul.s','fdiv.s',\
@ -11,8 +11,8 @@ instrs_fcsr_affected = ['fmadd.s','fmsub.s','fnmsub.s','fnmadd.s','fadd.s','fsub
'fcvt.s.lu', 'fmadd.d','fmsub.d','fnmsub.d','fnmadd.d','fadd.d','fsub.d',\
'fmul.d','fdiv.d','fsqrt.d','fmin.d','fmax.d','fcvt.s.d','fcvt.d.s',\
'feq.d','flt.d','fle.d','fcvt.w.d','fcvt.wu.d','fcvt.l.d','fcvt.lu.d',\
'fcvt.d.l','fcvt.d.lu']
unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','fsw','fsd',\
'fcvt.d.l','fcvt.d.lu','fadd.q','fsub.q','fmadd.q','fmsub.q','fnmsub.q','fnmadd.q']
unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','flq','fsw','fsd','fsq',\
'bgeu', 'bltu', 'sltiu', 'sltu','c.lw','c.ld','c.lwsp','c.ldsp',\
'c.sw','c.sd','c.swsp','c.sdsp','mulhu','divu','remu','divuw',\
'remuw','aes64ds','aes64dsm','aes64es','aes64esm','aes64ks2',\
@ -33,9 +33,9 @@ unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\
'xperm.n','xperm.b', 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi',\
'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig1h','sha512sig0l','sha512sig0h','fsw',\
'bclr','bext','binv','bset','minu','maxu','add.uw','sh1add.uw','sh2add.uw','sh3add.uw']
f_instrs_pref = ['fadd', 'fclass', 'fcvt', 'fdiv', 'feq', 'fld', 'fle', 'flt', 'flw', 'fmadd',\
f_instrs_pref = ['fadd', 'fclass', 'fcvt', 'fdiv', 'feq', 'fld','flq', 'fle', 'flt', 'flw', 'fmadd',\
'fmax', 'fmin', 'fmsub', 'fmul', 'fmv', 'fnmadd', 'fnmsub', 'fsd', 'fsgnj', 'fsqrt',\
'fsub', 'fsw']
'fsub', 'fsw','fsq']
instr_var_evaluator_funcs = {} # dictionary for holding registered evaluator funcs
@ -146,6 +146,8 @@ class instructionObject():
instr_vars['iflen'] = 32
elif self.instr_name.endswith(".d"):
instr_vars['iflen'] = 64
elif self.instr_name.endswith(".q"):
instr_vars['iflen'] = 128
# capture the operands
if self.rs1 is not None:
@ -179,6 +181,8 @@ class instructionObject():
ea_align = (rs1_val + imm_val) % 4
if self.instr_name in ['ld','sd','fld','fsd']:
ea_align = (rs1_val + imm_val) % 8
if self.instr_name in ['flq','fsq']:
ea_align = (rs1_val + imm_val) % 16
instr_vars.update({
'rs1_val': rs1_val,
@ -439,9 +443,12 @@ class instructionObject():
if iflen == 32:
e_sz = 8
m_sz = 23
else:
elif iflen == 64:
e_sz = 11
m_sz = 52
elif iflen == 128:
e_sz = 15
m_sz = 112
bin_val = ('{:0'+str(flen)+'b}').format(reg_val)
if flen > iflen:

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/riscv_isac/cgf_normalize.py
View File

@ -43,7 +43,7 @@ def simd_val_comb(xlen, bit_width, signed=True):
:type signed: bool
'''
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd'}
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd', 128: 'q'}
sz = fmt[bit_width]
var_num = xlen//bit_width
coverpoints = []
@ -78,7 +78,7 @@ def simd_base_val(rs, xlen, bit_width, signed=True):
:type signed: bool
'''
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd'}
fmt = {8: 'b', 16: 'h', 32: 'w', 64: 'd', 128: 'q'}
sz = fmt[bit_width]
var_num = xlen//bit_width

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/riscv_isac/coverage.py
View File

@ -536,8 +536,10 @@ class archState:
if flen == 32:
self.f_rf = ['00000000']*32
else:
elif flen == 64:
self.f_rf = ['0000000000000000']*32
else:
self.f_rf = ['00000000000000000000000000000']*32
self.pc = 0
self.flen = flen

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/riscv_isac/data/rvopcodesdecoder.py
View File

@ -362,7 +362,7 @@ class disassembler():
if 'rs1' in arg:
treg = reg_type
if any([instr_name.startswith(x) for x in [
'fsw','fsd','fcvt.s','fcvt.d','fmv.w','fmv.l']]):
'fsw','fsd','fsq','fcvt.s','fcvt.d','fmv.w','fmv.l']]):
treg = 'x'
temp_instrobj.rs1 = (int(get_arg_val(arg)(mcode), 2), treg)
if 'rs2' in arg:

24
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/riscv_isac/plugins/internaldecoder.py
View File

@ -18,8 +18,8 @@ class disassembler():
0b0011011: self.rv64i_arithi_ops,
0b0111011: self.rv64i_arith_ops,
0b0101111: self.rv64_rv32_atomic_ops,
0b0000111: self.flw_fld,
0b0100111: self.fsw_fsd,
0b0000111: self.flw_fld_flq,
0b0100111: self.fsw_fsd_fsq,
0b1000011: self.fmadd,
0b1000111: self.fmsub,
0b1001011: self.fnmsub,
@ -1606,7 +1606,7 @@ class disassembler():
return instrObj
def flw_fld(self, instrObj):
def flw_fld_flq(self, instrObj):
instr = instrObj.instr
rd = ((instr & self.RD_MASK) >> 7, 'f')
rs1 = ((instr & self.RS1_MASK) >> 15, 'x')
@ -1621,10 +1621,12 @@ class disassembler():
instrObj.instr_name = 'flw'
elif funct3 == 0b011:
instrObj.instr_name = 'fld'
elif funct3 == 0b100:
instrObj.instr_name = 'flq'
return instrObj
def fsw_fsd(self, instrObj):
def fsw_fsd_fsq(self, instrObj):
instr = instrObj.instr
imm_4_0 = (instr & self.RD_MASK) >> 7
imm_11_5 = (instr >> 25) << 5
@ -1642,6 +1644,8 @@ class disassembler():
instrObj.instr_name = 'fsw'
elif funct3 == 0b011:
instrObj.instr_name = 'fsd'
elif funct3 == 0b100:
instrObj.instr_name = 'fsq'
return instrObj
@ -1766,6 +1770,14 @@ class disassembler():
instrObj.instr_name = 'fmul.d'
elif funct7 == 0b0001101:
instrObj.instr_name = 'fdiv.d'
elif funct7 == 0b0000011:
instrObj.instr_name = 'fadd.q'
elif funct7 == 0b0000111:
instrObj.instr_name = 'fsub.q'
elif funct7 == 0b0001011:
instrObj.instr_name = 'fmul.q'
elif funct7 == 0b0001111:
instrObj.instr_name = 'fdiv.q'
# fsqrt
if funct7 == 0b0101100:
@ -1776,6 +1788,10 @@ class disassembler():
instrObj.instr_name = 'fsqrt.d'
instrObj.rs2 = None
return instrObj
elif funct7 == 0b0101111:
instrObj.instr_name = 'fsqrt.q'
instrObj.rs2 = None
return instrObj
# fsgnj, fsgnjn, fsgnjx
if funct7 == 0b0010000: