David Harris
7868c0da55
Cleaning shifter
2021-12-18 09:43:09 -08:00
David Harris
b453454b24
Moved W64 truncation after result mux
2021-12-18 09:27:25 -08:00
David Harris
2a5a7eff82
Forwarding logic factoring
2021-12-18 05:40:38 -08:00
David Harris
1212e21eba
Simplified FWriteInt interfaces by merging into RegWrite
2021-12-18 05:36:32 -08:00
David Harris
da1df17fbb
Do File cleanups
2021-12-17 17:45:26 -08:00
Ross Thompson
2f86e84843
Merge remote-tracking branch 'origin/tlb_fixes' into main
2021-12-17 14:40:29 -06:00
Ross Thompson
79ec4161b6
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
5264577dcf
Possible fix for icache deadlock interaction with hptw.
2021-12-17 14:38:25 -06:00
David Harris
3a9071e509
Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
2021-12-15 12:10:45 -08:00
David Harris
f0059b7b3a
IEU cleanup:
2021-12-15 11:38:26 -08:00
Ross Thompson
9f798250ea
Oups missed files in the last commit.
2021-12-15 10:25:08 -06:00
David Harris
f4957fdac1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
David Harris
6b27e19381
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-14 13:05:47 -08:00
David Harris
b42faa794a
changed ideal memory to MEM_DTIM and MEM_ITIM
2021-12-14 13:05:32 -08:00
Ross Thompson
45b38ea9fe
Comments for dcache and icache refactoring.
2021-12-14 14:46:29 -06:00
David Harris
ee5c2e6101
renamed rv32/64g to rv32/64gc in configuration
2021-12-14 11:22:00 -08:00
David Harris
eb33021f40
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-14 11:15:58 -08:00
David Harris
dd0d4c0add
ALU and datapath cleanup
2021-12-14 11:15:47 -08:00
Ross Thompson
5e4e44a2cc
Added patch file for the qemu modifications.
...
Added instructions for building and installing qemu.
2021-12-13 18:36:00 -06:00
Ross Thompson
f061a26411
Cleaned up fpga synthesis script.
2021-12-13 18:26:54 -06:00
Ross Thompson
b9c8b808ea
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-13 17:16:20 -06:00
Ross Thompson
7d00649b61
Formating changes to cache fsms.
2021-12-13 17:16:13 -06:00
Ross Thompson
5361f69639
Fixed some typos in the dcache ptw interaction documentation.
2021-12-13 15:47:20 -06:00
David Harris
74cf0eb96a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-13 07:57:49 -08:00
David Harris
1ca949c0bb
Simplified ALU and source multiplexers pass tests
2021-12-13 07:57:38 -08:00
kwan
5ede8126fd
priviledge .* removed, passed regression
2021-12-13 00:34:43 -08:00
kwan
b05bc3c19e
test
2021-12-13 00:31:51 -08:00
kwan
83dae9d774
priviledge .* fixed, passed local regression
2021-12-13 00:22:01 -08:00
Kevin
3aad1137c2
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-12 17:53:41 -08:00
Kevin
b928d01bb8
dot stars conversions on the rest of the testbenches
2021-12-12 17:53:26 -08:00
Ross Thompson
8e39034dbd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-12 17:33:29 -06:00
Ross Thompson
2f282e5570
Revert "Privilige .*s removed"
...
This reverts commit 471f267987
2021-12-12 17:31:57 -06:00
Ross Thompson
fdbb7b6ef3
Revert "Priviledged .* removed"
...
This reverts commit 96ac298596
2021-12-12 17:31:39 -06:00
Ross Thompson
547093b705
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-12 17:21:51 -06:00
Ross Thompson
bb79f70a63
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
b88ec949cf
Added proper credit to Richard Davis, the author of the original sd card reader.
2021-12-12 15:05:50 -06:00
kwan
96ac298596
Priviledged .* removed
2021-12-12 09:55:45 -08:00
kwan
471f267987
Privilige .*s removed
2021-12-12 09:54:14 -08:00
David Harris
d3c3ab3e85
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-12 05:49:31 -08:00
Kevin
78fbe542a9
edited one testbench, yet to run regression
2021-12-10 20:26:20 -08:00
Ross Thompson
c688b27a20
Performance counters now output of coremark.
2021-12-09 14:48:17 -06:00
Ross Thompson
cd59809e42
Fixed numerous errors in the preformance counter updates.
...
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
2021-12-09 11:44:12 -06:00
bbracker
4bc4930ff3
fix recursive signal logging for graphical sims
2021-12-08 16:07:26 -08:00
bbracker
64652be7c5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 14:12:18 -08:00
bbracker
c97e96f553
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 14:12:09 -08:00
bbracker
6a6835ddc3
fix release of ReadDataM
2021-12-08 14:11:43 -08:00
slmnemo
3ff994f50d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
...
help
2021-12-08 14:09:58 -08:00
slmnemo
094f45e28b
Removed .* from /wally-pipelined/src/uncore/uart.sv
2021-12-08 14:02:53 -08:00
Ross Thompson
a55018b67a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-08 15:50:43 -06:00
Ross Thompson
3bdda9687a
Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict.
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Remove preload from dtim.
2021-12-08 15:50:15 -06:00
David Harris
9e2c3bef3c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 13:48:49 -08:00
David Harris
0b63c1cede
Refactored IEU/ALU logic
2021-12-08 13:48:04 -08:00
Noah Limpert
e97dd080a0
updated fcmp.sv instantiation to remove x*'s
2021-12-08 13:34:33 -08:00
David Harris
a174c8b4d7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 12:33:59 -08:00
David Harris
5d4014d351
Refactoring ALU and datapath muxes
2021-12-08 12:33:53 -08:00
Ross Thompson
37451b8978
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-08 13:40:44 -06:00
Ross Thompson
e1249f4312
Updated coremark testbench with the extra ports from FPGA merge.
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Fixed coremark Makefile to create work directory.
2021-12-08 13:40:32 -06:00
bbracker
4060e77b56
increase regression's expectations of buildroot to 246 million
2021-12-08 07:01:22 -08:00
slmnemo
d58f318d39
Removed .*s from wally-pipelined/src/uncore/uncore.sv
2021-12-08 01:03:02 -08:00
slmnemo
52b4802600
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 00:26:13 -08:00
Noah Limpert
feb21d1c4a
removed .* instantiation from ieu.sv and datapth.sv in ieu folder
2021-12-08 00:24:27 -08:00
slmnemo
acacd13ffc
Removed .* from mmu instance inside lsu.sv.
2021-12-08 00:15:30 -08:00
Katherine Parry
d0e708f239
FMA uses one LOA
2021-12-07 14:15:43 -08:00
bbracker
d459e35645
undo intentionally breaking commit
2021-12-07 13:43:47 -08:00
bbracker
3379b74bb2
intentionally breaking commit
2021-12-07 13:27:34 -08:00
bbracker
cf61187273
undo intentionally breaking commit
2021-12-07 13:27:06 -08:00
bbracker
69f025a642
intentionally breaking commit
2021-12-07 13:23:19 -08:00
bbracker
ec6c3bd74c
2nd attempt at making regression-wally.py able to be run from a different dir
2021-12-07 13:13:30 -08:00
bbracker
0c48725fa5
fix checkpointing so that it can find the synchronized reset signal
2021-12-07 13:12:06 -08:00
bbracker
9fc4f3bfef
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-07 11:16:51 -08:00
bbracker
0692372037
attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly
2021-12-07 11:16:43 -08:00
Ross Thompson
51e2b9ea6f
Added information on how to copy the linux image to flash card.
2021-12-07 13:16:38 -06:00
bbracker
8e2a9d5bbb
add buildroot tv linking to make-tests.sh
2021-12-07 11:15:59 -08:00
Ross Thompson
c7be8a701e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-07 13:12:59 -06:00
Ross Thompson
8bb3d51aad
Added generate around the dtim preload.
...
Added readme to explain FPGA.
2021-12-07 13:12:47 -06:00
Ross Thompson
3d829dbbd3
Fixed two issues.
...
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
bbracker
ffe7cf83e5
regression.py bugfix
2021-12-06 19:32:38 -08:00
bbracker
b714490f92
add make-tests scripts
2021-12-06 15:37:33 -08:00
bbracker
d702599d56
add buildroot-only option to regression
2021-12-06 14:13:58 -08:00
bbracker
6c9db52801
linux-testvectors symlinks shouldn't be in repo, especially not in this location
2021-12-05 22:03:51 -08:00
Ross Thompson
517cae796c
Fixed more constraint issues in fpga.
...
Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
David Harris
19fb0aace8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-04 20:26:01 -08:00
David Harris
83765ea3bc
Added files to repo
2021-12-04 20:25:33 -08:00
Skylar Litz
a69ab3bd1b
fix some interrupt timing bugs
2021-12-03 12:32:38 -08:00
Ross Thompson
755c3e6a4c
Fixed buildroot to work with the fpga's merge.
2021-12-02 18:09:43 -06:00
Ross Thompson
74ffb48c0a
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
2021-12-02 18:00:32 -06:00
Ross Thompson
b7e8c74e61
Merge branch 'fpga' into main
2021-12-02 14:28:10 -06:00
kwan
e4f214090d
.* resolved in ifu.sv
2021-12-02 10:32:35 -08:00
kwan
2a77bc8053
.* in ifu/ifu.sv eliminated
2021-12-02 09:45:55 -08:00
David Harris
e4861e11d1
Added coremark scripts to regression directory
2021-12-01 09:08:06 -08:00
David Harris
273e211660
testing push
2021-11-30 11:20:09 -08:00
Ross Thompson
d7df9c1054
Fixed uart for FPGA config after merge. This still needs some work.
2021-11-29 16:07:54 -06:00
Ross Thompson
8e4eacc18e
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
c5d393fbc6
UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
2021-11-25 11:01:59 -08:00
Noah Limpert
cb77c1db3a
updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well
2021-11-24 23:22:04 -08:00
Noah Limpert
e66fdd3f80
replaced .* instation of priv module on wallypiplinedhart
2021-11-24 22:58:59 -08:00
Noah Limpert
0cd31bfc1f
Made abhlite instation on wallypipehart more clear, updated spacing for consistency
2021-11-24 22:48:01 -08:00
Noah Limpert
8a64510ee4
updated module instation of LSU on wallypiplinedhard
2021-11-24 22:09:39 -08:00
bbracker
de8e2008d2
fix parseState.py to correctly take in PMPCFG
2021-11-24 16:52:51 -08:00
Ross Thompson
b909375289
Missed another change to uart.
2021-11-23 10:20:47 -06:00
Ross Thompson
fe00729d7c
Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.
2021-11-23 10:00:32 -06:00
Ross Thompson
e309017ec4
Added QEMU hack for initial LCR value in uart.
2021-11-22 15:23:19 -06:00
Ross Thompson
e568068c78
Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed.
2021-11-22 15:20:54 -06:00
Ross Thompson
fcd14828d4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-22 11:30:14 -06:00
bbracker
d90d708cf9
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
Ross Thompson
c661bb4894
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:44:45 -06:00
Ross Thompson
d080041508
Removed unneeded check for icache ways.
2021-11-20 22:44:37 -06:00
Ross Thompson
baa98e7015
Reversed bit order in uart.
2021-11-20 22:43:05 -06:00
Ross Thompson
4443fca5c5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:37:15 -06:00
Ross Thompson
2f85ac7f38
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
...
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
bbracker
9e4033935f
add checkpoints to regression
2021-11-20 19:42:53 -08:00
bbracker
685534fc20
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-19 20:25:06 -08:00
bbracker
42ba205c4f
automatic bug finder script
2021-11-19 20:25:00 -08:00
bbracker
5a2a2ca4f5
increase buildroot progress expecttions; increase timeout to 20 hours
2021-11-19 12:52:11 -08:00
David Harris
fb3f267645
Coremark Cleanup, trying compile from addins
2021-11-19 06:09:04 -08:00
David Harris
c45f276f86
Moved exe2memfile.pl
2021-11-18 20:32:13 -08:00
David Harris
d243f4bcd1
Cleaning up CoreMark benchmark
2021-11-18 20:12:52 -08:00
David Harris
54fef3e2ca
vert "Simplifying riscv-coremark"
...
This reverts commit bdc212cf88
2021-11-18 18:40:13 -08:00
David Harris
bdc212cf88
Simplifying riscv-coremark
2021-11-18 17:15:40 -08:00
David Harris
f2cf09dd76
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-18 16:14:42 -08:00
David Harris
b996598b37
CoreMark testing
2021-11-18 16:14:25 -08:00
slmnemo
870549c01a
Removed .* from hazard hzu(.*).
2021-11-17 14:21:23 -08:00
slmnemo
a98dcd11ee
Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.
2021-11-17 14:08:08 -08:00
slmnemo
fed613dc72
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:38:51 -08:00
slmnemo
f4380faa4e
removed .* from muldiv.sv (REAL)
2021-11-17 13:37:50 -08:00
David Harris
b49c419d0b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:28:33 -08:00
Noah Limpert
0ccc7d5fe8
ieu variable naming changed for clarity
2021-11-17 13:24:28 -08:00
slmnemo
9fb26d5a61
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:23:20 -08:00
slmnemo
573f8b0c42
Removed .*s from muldiv.sv
2021-11-17 13:23:12 -08:00
Noah Limpert
ed2285b8e7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:04:33 -08:00
Noah Limpert
832b23b8a4
Updated IFU variable naming for clarity
2021-11-17 12:39:05 -08:00
Kevin Kim
d4e9376854
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 12:18:25 -08:00
Kevin Kim
34b3cc1c8d
root level makefile added
2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
3f76549a7d
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
Ross Thompson
3b8bdc7b2d
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
2021-11-17 12:47:19 -06:00
Ross Thompson
11a21899d5
Fixed uart by reversing the bit order on transmit.
...
Set prescale to 0.
2021-11-17 10:32:41 -06:00
Skylar Litz
e35faa9b8a
fixed interrupt timing bug
2021-11-16 16:46:17 -08:00
David Harris
5a521e28ee
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-16 12:30:55 -08:00
bbracker
23bd24323b
get current privilege level from GDB for checkpoints
2021-11-15 14:49:00 -08:00
Ross Thompson
4af7a27d87
Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing.
2021-11-12 17:37:07 -06:00
Ross Thompson
b8572d6a2a
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Skylar Litz
99a15e7897
fix timing of delayed interrupt
2021-11-11 09:35:51 -08:00
David Harris
f96152fa31
bringing Coremark back to life
2021-11-10 12:43:31 -08:00
Kevin Kim
a7684f1b59
Makefile added in regression directory:
...
-cd's into imperas then runs make commands, finally running the tvLinker script
2021-11-09 10:55:48 -08:00
bbracker
1597e0dac6
increase expectations for buildroot and timeout count
2021-11-06 14:57:29 -07:00
bbracker
24d3244cfe
checkpoint MIDELEG support
2021-11-06 03:44:23 -07:00
bbracker
1d3d7cbe1e
fix merge conflict
2021-11-05 23:42:15 -07:00
bbracker
3077769cbd
checkpoints now use binary ram files
2021-11-05 22:37:05 -07:00
Kevin
b34569c358
changed code aligner to run recursively on a root directory
...
-only runs the aligner on .sv files
-runs recursively on sub-directories
2021-11-03 10:49:34 -07:00
