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1969 Commits

Author SHA1 Message Date
David Harris
e97e512da9 Started FIR test code and started incorporating Imperas tests 2021-12-25 22:39:51 +00:00
David Harris
35e31006a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-25 06:37:30 -08:00
David Harris
37b091e5da Checked in Chapter 2 C and assembly examples 2021-12-25 06:35:36 -08:00
Ross Thompson
ae0cc085b4 Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages. 
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.

There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment.  This can be cached in the TLB which only costs 1 flip flop
   for each TLB line.
 2021-12-23 12:40:22 -06:00
Ross Thompson
42ad710213 linux-wave.do changes. 2021-12-21 22:37:55 -06:00
Ross Thompson
50e4463a7f It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register. 2021-12-21 15:59:56 -06:00
Ross Thompson
4ae15bf5e4 Fixed bug where the wrong address is read into the icache memory. 2021-12-21 15:16:00 -06:00
Ross Thompson
0a7dc96052 Fixed complex bug where FENCE is instruction class miss predicted as a taken branch. 2021-12-21 11:29:28 -06:00
Ross Thompson
b0507b96b0 Identified bug in the IFU which selects PCNextF when InvalidateICacheM is true. If the ID is invalid PCNextF should NOT be PCE. 2021-12-20 23:45:55 -06:00
Ross Thompson
a02ac78907 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-20 23:27:46 -06:00
Ross Thompson
0bc3bcf406 Fixed bug on icache spill. if the cpu stalled on the completion it was possible to use the wrong address for the sram read. Also miss spill hit always selected the wrong address. 2021-12-20 23:27:37 -06:00
David Harris
0c57b61ace Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-20 21:09:20 -08:00
David Harris
001c39d8eb Fixing paths in wally-setup.sh 2021-12-20 21:08:34 -08:00
Ross Thompson
47638cdccf Looks like rdtime was accidentally replaced with rrame from a find and replace. 2021-12-20 21:26:38 -06:00
Ross Thompson
d830721a11 Fixed Type 5b interaction between dcache and hptw. 
This is a load concurrent with ITLBMiss.
 2021-12-20 18:33:31 -06:00
Ross Thompson
6aff6b0fa3 Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM. 2021-12-20 10:03:56 -06:00
Ross Thompson
53736096a6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-20 10:03:19 -06:00
Ross Thompson
b261b18aa8 More signal name cleanup in LSU. 2021-12-19 22:47:48 -06:00
Ross Thompson
533c2f3556 Remove verbosity from lsu state machine. 2021-12-19 22:41:34 -06:00
Ross Thompson
82dd41a0fd Rename of SelPTW to SelHPTW. 2021-12-19 22:24:07 -06:00
Ross Thompson
9c2fc30507 Signal renames. 2021-12-19 22:21:03 -06:00
Ross Thompson
2f5de7eb82 Hardware reductions in the lsu. 2021-12-19 22:00:28 -06:00
Ross Thompson
035ce99938 Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent. 2021-12-19 21:36:54 -06:00
Ross Thompson
30770db4ac Removed lsuArb and placed remaining logic in lsu.sv. 
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
 2021-12-19 21:34:40 -06:00
Ross Thompson
db76878581 Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card. 
mv qemu patches to tests directory.
 2021-12-19 20:11:32 -06:00
David Harris
193885c958 Moved generate of conditional units to hart 2021-12-19 17:03:57 -08:00
David Harris
1196e5c191 Moved generate statements for optional units into wallypipelinedhart 2021-12-19 16:53:41 -08:00
Ross Thompson
7b2f5440a5 Changes to buildroot to support MemAdrM to IEUAdrM name changes. 2021-12-19 18:24:40 -06:00
Ross Thompson
aeb8c94df1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-19 18:16:49 -06:00
Ross Thompson
cef4b6399d Switched to using an always block for lsu stall logic. This avoids the problematic x propagation. 2021-12-19 18:16:08 -06:00
Ross Thompson
814bcec7b7 Implemented what I think is the last required change for the lsu state machine. 2021-12-19 17:57:12 -06:00
Ross Thompson
54fd8678b0 Created hack to get around imperas64mmu unknown (value = x) bug. 2021-12-19 17:53:13 -06:00
Ross Thompson
13f0e9bafa Fixed bug where icache did not replay PCF on itlb miss. 2021-12-19 17:01:13 -06:00
Ross Thompson
04d0b85f96 Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass. 2021-12-19 16:12:31 -06:00
David Harris
5e1c3e322b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-19 13:53:53 -08:00
David Harris
691c1c0dd0 ALUControl cleanup 2021-12-19 13:53:45 -08:00
Katherine Parry
ece9e9df84 fixed some small errors in FMA 2021-12-19 13:51:46 -08:00
Ross Thompson
202203904c Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm. 2021-12-19 15:10:33 -06:00
Ross Thompson
9adcf86a40 Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage. 
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
 2021-12-19 14:57:42 -06:00
Ross Thompson
0257c08641 Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache. 2021-12-19 14:00:30 -06:00
Ross Thompson
620f4a58d4 Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states. 2021-12-19 13:55:57 -06:00
Ross Thompson
fdf493bd47 minro change. comments about needed changes in dcache. 2021-12-19 13:53:02 -06:00
David Harris
c04c56dae1 Renamed zero to eq in flag generation 2021-12-19 11:49:15 -08:00
David Harris
e5d2d7a3fd Controller fix 2021-12-18 22:08:23 -08:00
David Harris
8a597390e0 Renamed RD1D to R1D, etc. 2021-12-18 21:26:00 -08:00
David Harris
7fb4213751 Simplified shifter right input 2021-12-18 10:25:40 -08:00
Ross Thompson
f601b3ae53 Merge branch 'tlb_fixes' into main 2021-12-18 12:24:17 -06:00
David Harris
d97d34ee32 Simplified Shifter Right input 2021-12-18 10:21:17 -08:00
David Harris
852c521328 Shared ALU mux input for shifts 2021-12-18 10:08:52 -08:00
David Harris
a7d7f852a6 Factored out common parts of shifter 2021-12-18 10:01:12 -08:00
David Harris
7868c0da55 Cleaning shifter 2021-12-18 09:43:09 -08:00
David Harris
b453454b24 Moved W64 truncation after result mux 2021-12-18 09:27:25 -08:00
David Harris
2a5a7eff82 Forwarding logic factoring 2021-12-18 05:40:38 -08:00
David Harris
1212e21eba Simplified FWriteInt interfaces by merging into RegWrite 2021-12-18 05:36:32 -08:00
David Harris
da1df17fbb Do File cleanups 2021-12-17 17:45:26 -08:00
Ross Thompson
2f86e84843 Merge remote-tracking branch 'origin/tlb_fixes' into main 2021-12-17 14:40:29 -06:00
Ross Thompson
79ec4161b6 Added more debugging code for FPGA. 2021-12-17 14:40:25 -06:00
Ross Thompson
5264577dcf Possible fix for icache deadlock interaction with hptw. 2021-12-17 14:38:25 -06:00
David Harris
3a9071e509 Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies 2021-12-15 12:10:45 -08:00
David Harris
f0059b7b3a IEU cleanup: 2021-12-15 11:38:26 -08:00
Ross Thompson
9f798250ea Oups missed files in the last commit. 2021-12-15 10:25:08 -06:00
David Harris
f4957fdac1 Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
David Harris
6b27e19381 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-14 13:05:47 -08:00
David Harris
b42faa794a changed ideal memory to MEM_DTIM and MEM_ITIM 2021-12-14 13:05:32 -08:00
Ross Thompson
45b38ea9fe Comments for dcache and icache refactoring. 2021-12-14 14:46:29 -06:00
David Harris
ee5c2e6101 renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
David Harris
eb33021f40 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-14 11:15:58 -08:00
David Harris
dd0d4c0add ALU and datapath cleanup 2021-12-14 11:15:47 -08:00
Ross Thompson
5e4e44a2cc Added patch file for the qemu modifications. 
Added instructions for building and installing qemu.
 2021-12-13 18:36:00 -06:00
Ross Thompson
f061a26411 Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
Ross Thompson
b9c8b808ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-13 17:16:20 -06:00
Ross Thompson
7d00649b61 Formating changes to cache fsms. 2021-12-13 17:16:13 -06:00
Ross Thompson
5361f69639 Fixed some typos in the dcache ptw interaction documentation. 2021-12-13 15:47:20 -06:00
David Harris
74cf0eb96a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-13 07:57:49 -08:00
David Harris
1ca949c0bb Simplified ALU and source multiplexers pass tests 2021-12-13 07:57:38 -08:00
kwan
5ede8126fd priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
kwan
b05bc3c19e test 2021-12-13 00:31:51 -08:00
kwan
83dae9d774 priviledge .* fixed, passed local regression 2021-12-13 00:22:01 -08:00
Kevin
3aad1137c2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 17:53:41 -08:00
Kevin
b928d01bb8 dot stars conversions on the rest of the testbenches 2021-12-12 17:53:26 -08:00
Ross Thompson
8e39034dbd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:33:29 -06:00
Ross Thompson
2f282e5570 Revert "Privilige .*s removed" 
This reverts commit 471f267987.
 2021-12-12 17:31:57 -06:00
Ross Thompson
fdbb7b6ef3 Revert "Priviledged .* removed" 
This reverts commit 96ac298596.
 2021-12-12 17:31:39 -06:00
Ross Thompson
547093b705 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:21:51 -06:00
Ross Thompson
bb79f70a63 Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language. 2021-12-12 17:21:44 -06:00
Ross Thompson
b88ec949cf Added proper credit to Richard Davis, the author of the original sd card reader. 2021-12-12 15:05:50 -06:00
kwan
96ac298596 Priviledged .* removed 2021-12-12 09:55:45 -08:00
kwan
471f267987 Privilige .*s removed 2021-12-12 09:54:14 -08:00
David Harris
d3c3ab3e85 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 05:49:31 -08:00
Kevin
78fbe542a9 edited one testbench, yet to run regression 2021-12-10 20:26:20 -08:00
Ross Thompson
c688b27a20 Performance counters now output of coremark. 2021-12-09 14:48:17 -06:00
Ross Thompson
cd59809e42 Fixed numerous errors in the preformance counter updates. 
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
 2021-12-09 11:44:12 -06:00
bbracker
4bc4930ff3 fix recursive signal logging for graphical sims 2021-12-08 16:07:26 -08:00
bbracker
64652be7c5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 14:12:18 -08:00
bbracker
c97e96f553 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 14:12:09 -08:00
bbracker
6a6835ddc3 fix release of ReadDataM 2021-12-08 14:11:43 -08:00
slmnemo
3ff994f50d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
help
 2021-12-08 14:09:58 -08:00
slmnemo
094f45e28b Removed .* from /wally-pipelined/src/uncore/uart.sv 2021-12-08 14:02:53 -08:00
Ross Thompson
a55018b67a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-08 15:50:43 -06:00
Ross Thompson
3bdda9687a Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict. 
Remove preload from dtim.
 2021-12-08 15:50:15 -06:00