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Author SHA1 Message Date
Ross Thompson
c000366d3e closer, but the wally32/64priv tests are failing. 2023-07-05 17:47:38 -05:00
Ross Thompson
98147e116a Partially solved fpga boot. 2023-07-05 17:30:55 -05:00
Ross Thompson
7aecd72c35 Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits. 2023-06-22 12:55:49 -05:00
Ross Thompson
a8f11dcad0 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
af187d96ca Updated fpga wave config. 2023-06-19 12:28:30 -05:00
Ross Thompson
1a23f1360f Updated fpga wally wrapper to work with the ILA. 2023-06-19 12:15:48 -05:00
Ross Thompson
f5cee3fb66 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
Ross Thompson
cde2b1f2d2 Merge pull request #344 from davidharrishmc/dev 
Embench and coverage fixes
 2023-06-18 17:36:37 -04:00
David Harris
5d6eb40c2d Fixed embench to run all tests, even ones not in 1.0 2023-06-17 20:38:51 -07:00
David Harris
46b83ad6a4 Merge pull request #343 from harshinisrinath1001/main 
Improve test coverage on ieu fw.
 2023-06-16 16:11:51 -07:00
harshinisrinath
d018357914 Improve test coverage on ieu fw. 2023-06-16 16:09:48 -07:00
David Harris
2db94e7ddd Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete 2023-06-16 16:07:28 -07:00
David Harris
c383407d5c Removed redundant and not-covered atomic check from StoreStallD 2023-06-16 16:05:53 -07:00
Ross Thompson
0423d7df82 I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug. 2023-06-16 17:00:27 -05:00
Ross Thompson
443c568994 Vivado requires an intermediate wrapper file for parameterization. 2023-06-16 16:30:14 -05:00
Ross Thompson
c44d4321fb FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. 2023-06-16 15:40:13 -05:00
David Harris
b1bfba7995 erge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:32:37 -07:00
David Harris
ea1f731cd5 Merge pull request #342 from ross144/main 
Testbench generates embench output files
 2023-06-16 10:32:18 -07:00
Ross Thompson
7f79c0a855 Modified the testbench to generate the required files for embench scripts. 2023-06-16 12:27:22 -05:00
David Harris
924a3ea3cf Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:03:48 -07:00
David Harris
ba2ee7453b Merge pull request #341 from ross144/main 
Fix embench so it does not crash
 2023-06-16 10:03:41 -07:00
Ross Thompson
4d76e83318 embench testbench no longer crashes. 2023-06-16 11:54:41 -05:00
David Harris
c2913f49a3 Added assertions for ZICNTR and ZIHPM 2023-06-16 09:26:02 -07:00
David Harris
f62ac5d591 Merge pull request #340 from eroom1966/main 
Incorporate changes for IDV
 2023-06-16 09:04:55 -07:00
David Harris
1d70f43257 Merge pull request #339 from ross144/main 
Fixed imperas testbench to work with parameters
 2023-06-16 09:04:39 -07:00
eroom1966
5f358d1af7 add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
Lee Moore
e96f0fc7ad Merge pull request #4 from ross144/main 
PR from Ross
 2023-06-16 15:24:07 +01:00
Ross Thompson
26f9d1edae Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-16 08:59:59 -05:00
Ross Thompson
d46500bfe0 Fixed the imperas testbench to work with parameters. 2023-06-16 08:59:52 -05:00
David Harris
49191c63c1 Merge pull request #338 from ross144/main 
First pass at testbench restructuring
 2023-06-15 14:36:28 -07:00
Ross Thompson
f3d35f914a Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
bdc5656ef3 Added comment to uart LCR to check reset value after updating FPGA. 2023-06-15 15:39:51 -05:00
Ross Thompson
4428babda9 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
7ef821a70b Merge pull request #333 from davidharrishmc/dev 
cvw.sv moved to root to avoid warnings; UART cleanup and QEMU removal
 2023-06-15 16:28:21 -04:00
Ross Thompson
d2219023c3 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
Ross Thompson
af046d4772 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
David Harris
3ca271b6a7 Added input gating on FPU 2023-06-15 12:38:33 -07:00
David Harris
9e839988dc Gated MDU to save power; doesn't seem to have affected simulation time 2023-06-15 12:17:23 -07:00
David Harris
9f88848832 Bit manipulation comment cleanup 2023-06-15 12:16:46 -07:00
Ross Thompson
87fb9a3e16 Deleted remaining old configs except fpga as I still need to create the parameterized version. 2023-06-15 14:08:13 -05:00
Ross Thompson
75b5c23edd Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
David Harris
a62211bad1 Gated inputs to BMU when inactive to save power and simulation time 2023-06-15 11:56:59 -07:00
Ross Thompson
009d8966e9 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
David Harris
d3aebc00d4 Fixed UART merge conflict 2023-06-15 11:36:37 -07:00
David Harris
8dbbf9201a Merge pull request #337 from harshinisrinath1001/main 
Fixed the spacing of the uncore and wally modules
 2023-06-15 11:33:29 -07:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Harshini Srinath
dd7c13cc2d Update wallypipelinedsoc.sv 
Program clean up
 2023-06-15 10:39:37 -07:00
Harshini Srinath
b4469fd3bf Update wallypipelinedcore.sv 
Program clean up
 2023-06-15 10:38:38 -07:00
Harshini Srinath
85a513e542 Update cvw.sv 
Program clean up
 2023-06-15 10:29:33 -07:00