Teo Ene
bd99a5613a
sky130 18T and 15T cell libraries removed
...
Upon noticing their size, concerns were raised about available drive space.
As 12T is the main implementation focus, the decision was made to remove 15T and 18T.
Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison.
2021-02-14 09:05:41 -06:00
Teo Ene
555e0296b2
After going through Lab 3 again, I've decided to make small changes to the provided floorplan so that it may serve as a slighly better example of a good floorplan.
2021-02-14 04:43:07 -06:00
Teo Ene
d6da36fbf6
Cleaning up my code a little bit more
2021-02-14 02:58:25 -06:00
Teo Ene
1ea01389b9
Final changes to the lab3 branch
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- Removed manual register file placement script, as it has been removed from lab.
- Created pre-sets that only have to be uncommented for the changing clock target portion of lab.
- Cleaned up Makefile in case anyone looks inside of it.
2021-02-14 02:01:20 -06:00
Teo Ene
5cc0d73aa0
Commiting sample floorplan that I failed to commit last night
2021-02-13 12:08:03 -06:00
Teo Ene
eab780afb9
- Cleaned up unnecessary files
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- Pulled updates for std cells
- Fixed typo that prevented easy switching between standard cell variants
- Fixed asynchronous reset paths from not being flagged as false
2021-02-12 21:49:42 -06:00
Teo Ene
2823bb1013
When Alex taught me how to use git, he stressed the importance of good commit messages that properly describe what changes were made
2021-02-12 16:52:23 -06:00
Teo Ene
9667f0f10f
Fixed rm bug for Ryan
2021-02-12 16:36:04 -06:00
Teo Ene
af3a888cde
Removed riscv-o3 module
2021-02-12 16:08:34 -06:00
Teo Ene
6c3c319d70
Quick commit for Ryan / branch / debugging.
2021-02-12 16:06:02 -06:00
Noah Boorstin
4bfed99da3
add reference output for some tests
2021-02-12 18:33:24 +00:00
bbracker
deb7780897
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Tejus Rao
fb6a4bbbf0
added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
2021-02-11 13:38:38 -05:00
Teo Ene
3e29e28132
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-02-10 20:49:12 -06:00
Teo Ene
5f84ed407c
Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
2021-02-10 20:48:39 -06:00
Teodor-Dumitru Ene
cdc96d306a
Added hex code for the pre-compiled, provided, CoreMark binary
2021-02-10 21:22:38 -05:00
Teo Ene
50d00acb31
Added freshly compiled CoreMark binaries (elf) and hex code (memfile) for the following extensions:
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- RV64I
2021-02-10 20:12:07 -06:00
ethan-falicov
7925fe3131
Fixed merge conflict stuff
2021-02-10 10:03:30 -05:00
ethan-falicov
06517631cc
More merge conflicts yay
2021-02-10 09:54:30 -05:00
ethan-falicov
863796b3c1
Merge conflict fixing
2021-02-10 09:45:47 -05:00
ethan-falicov
67662b888e
Adding I Type test cases from Lab 1
2021-02-10 09:39:43 -05:00
James E. Stine
475da788e2
Add ppt and mp4 of wavedrom usage
2021-02-09 13:15:29 -06:00
Jarred Allen
e334475ab5
Fix compile error in imperas testbench
2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
805817cda4
merge conflict?
2021-02-07 02:34:49 -05:00
Jarred Allen
29b7a0cd25
Actually run the WALLY-LOAD tests
2021-02-06 14:56:40 -05:00
Jarred Allen
a3f2f4c7bc
Add test vector set for load instructions
2021-02-06 13:05:59 -05:00
James E. Stine
493bab529e
Updates to wavedrom
2021-02-05 10:56:29 -06:00
bbracker
15c0b4af22
JAL testing
2021-02-05 08:08:42 -05:00
James E. Stine
a886e222c1
sorry ; last update
2021-02-04 15:20:15 -06:00
James E. Stine
44f0ac98b0
Update as overwrite a file :(
2021-02-04 15:11:06 -06:00
James E. Stine
f55dffadee
Updates to wavedrom for typos
2021-02-04 14:49:17 -06:00
James E. Stine
752552970c
Add some example wavedrom files - more on the way including ppt
2021-02-04 14:41:42 -06:00
Thomas Fleming
8d7a515ae7
Complete STORE tests
2021-02-04 15:38:22 -05:00
Brett Mathis
11e2666bb2
Parallel FSR's and F CTRL logic
2021-02-04 02:25:55 -06:00
Jarred Allen
088fbbcbf0
Change busybear test to use work-busybear library
2021-02-03 11:12:47 -05:00
Jarred Allen
f700efc2b3
Start on a test set for loads
2021-02-03 00:37:43 -05:00
David Harris
2a80bcf543
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 19:44:43 -05:00
David Harris
756352f129
Minor tweaks
2021-02-02 19:44:37 -05:00
Jarred Allen
e5bd749e2a
Refactor regression test
2021-02-02 17:22:29 -05:00
Noah Boorstin
d2064987e9
Add busybear testbench to nightly regression checking
...
If you don't like how I did this please feel free to undo it
2021-02-02 22:05:35 +00:00
Noah Boorstin
b5f474d9f5
same thing but do that right this time
2021-02-02 21:47:15 +00:00
Noah Boorstin
6dd5c42d55
change undefined syntax in extend.sv
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don't need verilator execption anymore
2021-02-02 21:39:20 +00:00
David Harris
429f48e766
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
9f9c3bcece
Changed DTIM latency to 2 cycles
2021-02-02 14:22:12 -05:00
David Harris
616830a3f0
Cleaned up hazard interface
2021-02-02 13:53:13 -05:00
David Harris
587a343dac
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 13:42:35 -05:00
David Harris
229bde5953
Moved LoadStall generation to IEU
2021-02-02 13:42:23 -05:00
David Harris
bb83fda1d8
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
Jarred Allen
da43b2be53
Fix intermittent errors caused by weird library stuff
2021-02-02 11:20:09 -05:00
Jarred Allen
b57604f4e4
Add the regression logs and new regression byproducts to the gitignore
2021-02-02 10:43:41 -05:00
