Ross Thompson
bc6e776609
Converted mux4 to mux3 in dcache.
2021-12-29 10:58:02 -06:00
Ross Thompson
5ebaeb5d90
Simplified the dcache to bus address generation.
2021-12-29 10:46:48 -06:00
Ross Thompson
15f1627a31
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
29b3285c8e
Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters.
...
Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
2021-12-28 21:28:03 -06:00
Ross Thompson
d64fe4b1c1
LSU Bus FSM beautification.
2021-12-28 16:53:53 -06:00
Ross Thompson
a966764d88
Removed CommittedM as it is redundant with LSUStall.
2021-12-28 16:14:10 -06:00
Ross Thompson
7044277165
Changed the bus name between dcache and ebu.
2021-12-28 15:57:36 -06:00
Ross Thompson
fe5f016a16
Name changes for states in LSU.
2021-12-28 15:03:24 -06:00
Ross Thompson
c1789932a4
Added generate around virtual memory hardware in LSU.
2021-12-28 15:00:02 -06:00
Ross Thompson
daac21b3bd
Moved generate for lrsc to lsu.
2021-12-28 14:17:18 -06:00
Ross Thompson
b6f4efd458
More cleanup of dcache.
2021-12-28 14:12:18 -06:00
Ross Thompson
22bfc80e62
Additional cleanup of the LSU.
2021-12-28 13:59:07 -06:00
Ross Thompson
b4ab435bff
Major cleanup of the LSU.
2021-12-28 13:10:45 -06:00
Ross Thompson
c2b0e61466
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
Ross Thompson
77e8ba619e
Minor dcache cleanup.
2021-12-28 11:29:16 -06:00
Ross Thompson
d6960da90e
Moved all bus logic outside the dcache. Still needs cleanup.
2021-12-28 11:18:47 -06:00
Ross Thompson
44b63fc0ba
First cut at moving the dcache bus interface into the LSU.
...
Regression test does not run and there is a lot of cleanup to do.
2021-12-27 18:12:59 -06:00
Ross Thompson
3e7ec1e9a2
Moved dcache fetch logic outside the dcache except for the fsm.
2021-12-27 16:45:49 -06:00
Ross Thompson
3ee29785a4
Partial commit.
...
Moved AMO, SWW, and SWR outside the dcache.
Step 1 of separate the fetching logic from the caches.
2021-12-27 15:56:18 -06:00
Ross Thompson
50e4463a7f
It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.
2021-12-21 15:59:56 -06:00
Ross Thompson
d830721a11
Fixed Type 5b interaction between dcache and hptw.
...
This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
6aff6b0fa3
Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM.
2021-12-20 10:03:56 -06:00
Ross Thompson
53736096a6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
b261b18aa8
More signal name cleanup in LSU.
2021-12-19 22:47:48 -06:00
Ross Thompson
533c2f3556
Remove verbosity from lsu state machine.
2021-12-19 22:41:34 -06:00
Ross Thompson
82dd41a0fd
Rename of SelPTW to SelHPTW.
2021-12-19 22:24:07 -06:00
Ross Thompson
9c2fc30507
Signal renames.
2021-12-19 22:21:03 -06:00
Ross Thompson
2f5de7eb82
Hardware reductions in the lsu.
2021-12-19 22:00:28 -06:00
Ross Thompson
30770db4ac
Removed lsuArb and placed remaining logic in lsu.sv.
...
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
2021-12-19 21:34:40 -06:00
Ross Thompson
cef4b6399d
Switched to using an always block for lsu stall logic. This avoids the problematic x propagation.
2021-12-19 18:16:08 -06:00
Ross Thompson
814bcec7b7
Implemented what I think is the last required change for the lsu state machine.
2021-12-19 17:57:12 -06:00
Ross Thompson
54fd8678b0
Created hack to get around imperas64mmu unknown (value = x) bug.
2021-12-19 17:53:13 -06:00
Ross Thompson
04d0b85f96
Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
2021-12-19 16:12:31 -06:00
Ross Thompson
202203904c
Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm.
2021-12-19 15:10:33 -06:00
Ross Thompson
9adcf86a40
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
...
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
0257c08641
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
620f4a58d4
Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states.
2021-12-19 13:55:57 -06:00
Ross Thompson
f601b3ae53
Merge branch 'tlb_fixes' into main
2021-12-18 12:24:17 -06:00
Ross Thompson
2f86e84843
Merge remote-tracking branch 'origin/tlb_fixes' into main
2021-12-17 14:40:29 -06:00
Ross Thompson
79ec4161b6
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
5264577dcf
Possible fix for icache deadlock interaction with hptw.
2021-12-17 14:38:25 -06:00
David Harris
3a9071e509
Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
2021-12-15 12:10:45 -08:00
David Harris
f4957fdac1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
Ross Thompson
45b38ea9fe
Comments for dcache and icache refactoring.
2021-12-14 14:46:29 -06:00
slmnemo
acacd13ffc
Removed .* from mmu instance inside lsu.sv.
2021-12-08 00:15:30 -08:00
Ross Thompson
2f85ac7f38
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
...
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
Ross Thompson
87aaec3b6c
Partial cleanup of unused signals in caches and bpred.
2021-10-24 15:04:20 -05:00
David Harris
106982e493
more lsu/ifu lint cleanup
2021-10-23 12:10:13 -07:00
David Harris
8b1dc81d34
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
David Harris
88b2d9e687
lsu/ifu lint cleanup
2021-10-23 11:41:20 -07:00
