974 Commits

Author	SHA1	Message	Date
Katherine Parry	ba339fc794	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-11 18:30:29 -07:00
Katherine Parry	bea4ec078d	variable interations implemented in radix-4 divider	2022-07-11 18:30:21 -07:00
DTowersM	fe7d03a3da	added some preliminary support for coremark XLEN=32, made sure rv64 not impacted	2022-07-11 21:13:09 +00:00
David Harris	03a20610aa	added comment about checking SRAM size	2022-07-10 12:48:51 +00:00
David Harris	d1a7832dd9	added comment about RAMs in cacheway	2022-07-10 12:47:34 +00:00
cturek	0dc30a0acf	F Selection	2022-07-08 21:53:52 +00:00
Katherine Parry	c56fdd7e0f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-08 12:30:50 -07:00
Katherine Parry	88b4f9b40a	renamed signals in cvt and prostproc	2022-07-08 12:30:43 -07:00
James Stine	99fed5d59f	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00
David Harris	8be1dafbd6	Removed testbench code that ignores mismatch on zero signatures	2022-07-08 09:17:31 +00:00
David Harris	87ea95e6c5	erge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-08 09:09:07 +00:00
David Harris	5ae88dbef0	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
David Harris	96cc66d151	Adjusting byte writes to RAM	2022-07-08 08:45:21 +00:00
David Harris	38ef8eebbb	Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables	2022-07-08 08:44:37 +00:00
David Harris	234175f236	Removed unused swbytemask from CLINT	2022-07-08 08:43:24 +00:00
Katherine Parry	b67792086c	moved unsused division code again	2022-07-07 16:41:26 -07:00
cturek	ccc97d6fee	Sqrt exponents	2022-07-07 23:34:56 +00:00
Katherine Parry	2e772dee69	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-07 16:29:44 -07:00
Katherine Parry	b1e2a1e5a1	Revert "moved old divsqrt to unusedsrc" ... This reverts commit 5dd07c76bd.	2022-07-07 16:29:17 -07:00
DTowersM	4786fb9fd6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD	2022-07-07 23:11:35 +00:00
DTowersM	aa8580b2dc	new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory	2022-07-07 23:11:02 +00:00
Katherine Parry	5dd07c76bd	moved old divsqrt to unusedsrc	2022-07-07 16:09:56 -07:00
Katherine Parry	75a8cea4e4	srt divider merged into fpu	2022-07-07 16:01:33 -07:00
cturek	010ab2e90e	Seventeen Square Root Tests	2022-07-07 22:48:46 +00:00
David Harris	425fec0f41	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-07 22:00:59 +00:00
Katherine Parry	c581fba4aa	modified wally shared	2022-07-07 21:59:43 +00:00
David Harris	f865994ba1	fixing port errors	2022-07-07 21:57:10 +00:00
Katherine Parry	7771f7b3eb	added load and store test	2022-07-07 21:48:51 +00:00
cturek	269884b672	Preprocessing for square root	2022-07-07 21:23:30 +00:00
David Harris	f2915129ab	Preliminary SRAM integration	2022-07-07 19:56:20 +00:00
David Harris	bf5168873e	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-07 15:51:33 +00:00
slmnemo	261248538c	sim-buildroot-batch now runs wally-pipelined-batch ... with option buildroot buildroot-no-trace to boot linux from step 0	2022-07-06 18:06:43 -07:00
David Harris	8ae7139545	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-06 23:44:47 +00:00
DTowersM	5dfff900b1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD	2022-07-06 23:44:27 +00:00
DTowersM	67c5d66209	added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu	2022-07-06 23:43:57 +00:00
David Harris	21fb120aac	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-06 23:43:05 +00:00
Ross Thompson	d716c25275	Fixed an issue with direct map cache's nextway logic. ... Also found a small error in the replacement policy.	2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye	ad29e19a27	fixed width mismatch for rv64 ieuadrM and readdatawordM	2022-07-06 22:39:35 +00:00
David Harris	529f48ed58	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-06 13:26:26 +00:00
David Harris	76302a8599	PLIC and UART passing tests on APB	2022-07-06 13:26:14 +00:00
Madeleine Masser-Frye	52562c9190	new priority onehot module for better area/time	2022-07-06 00:08:59 +00:00
Madeleine Masser-Frye	b5454f3a55	took first match out of pmpadrdec	2022-07-06 00:02:01 +00:00
Madeleine Masser-Frye	d8ea12c6f4	fixed concatenation syntax	2022-07-05 22:36:54 +00:00
cturek	2faa8847f4	Radix 2 Integer division working (without signs or remainder)	2022-07-05 21:34:49 +00:00
David Harris	72e216d053	APB CLINT passing regression	2022-07-05 15:51:35 +00:00
David Harris	5f5ad77d4a	Modified uncore to use AHB bridge to GPIO	2022-07-05 05:02:21 +00:00
David Harris	c8ac05ba7b	AHB bridge for gpio	2022-07-05 05:01:59 +00:00
David Harris	ca95b46de5	Added reference to Schmookler01 for LOA	2022-07-05 05:01:12 +00:00
David Harris	1a356312b2	Added comments to PLIC about likely bug	2022-07-05 05:00:29 +00:00
David Harris	abfd935e06	removed delay in ahblite	2022-07-05 04:59:28 +00:00