bbracker
b3f00f2682
make testbench successfully deactivate TimerIntM so as to create a nice pulse
2021-09-07 15:36:47 -04:00
bbracker
28fed18421
No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
2021-09-06 22:59:54 -04:00
bbracker
a13b561759
modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations)
2021-09-04 19:49:26 -04:00
Ross Thompson
b7972eafeb
Added function tracking to linux test bench.
2021-08-24 11:08:46 -05:00
Ross Thompson
97653e1aea
Wally previously was overcounting retired instructions when they were flushed.
...
InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
2021-08-23 12:24:03 -05:00
Ross Thompson
b6e2710f5d
Confirmed David's changes to the interrupt code.
...
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine. This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege. Since the CPU
is currently in machine mode the interrupt must be taken if MIE.
Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
2021-08-22 21:36:31 -05:00
Ross Thompson
4eca94268c
Added logic to linux test bench to not stop simulation on csr write faults.
2021-08-15 11:13:32 -05:00
Ross Thompson
4f3f26c5cb
Switched ExceptionM to dcache to be just exceptions.
...
Added test bench logic to hold forces until the W stage is unstalled.
2021-08-13 15:53:50 -05:00
Ross Thompson
492b6f0ea4
Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token.
2021-08-13 14:53:43 -05:00
Ross Thompson
a1c26a16d6
Cleaned up the linux testbench by removing old code and signals.
...
Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
2021-08-13 14:39:05 -05:00
Ross Thompson
3b327c949f
Minor cleanup of the linux test bench.
2021-08-12 11:14:55 -05:00
Ross Thompson
467e24c05c
Fixed another bug with the atomic instrucitons implemention in the dcache.
2021-08-08 22:50:31 -05:00
Ross Thompson
25533bdc49
Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.
...
Fixed logic for trace update in the M and W stages. The M stage should not update if there
is an instruction fault.
2021-08-08 00:28:18 -05:00
Ross Thompson
fda9985382
Finally past the CLINT issues.
2021-08-06 16:41:34 -05:00
Ross Thompson
839822d3b1
Now past the CLINT issues.
2021-08-06 16:16:39 -05:00
Ross Thompson
e1319a2fbe
Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.
2021-08-06 16:06:50 -05:00
Ross Thompson
d430659983
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
Ross Thompson
722d298c35
Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.
2021-08-05 16:49:03 -05:00
Ross Thompson
245e7014b3
Added some comments to linux testbench.
2021-07-30 17:57:03 -05:00
Ross Thompson
cd8a66353c
Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files.
2021-07-30 14:24:50 -05:00
Ross Thompson
ef66cdeecf
Moved the test bench modules to a common directory.
2021-07-30 14:16:14 -05:00
Ross Thompson
b9f8c25280
Created new linux test bench and parsing scripts.
2021-07-29 20:26:50 -05:00
bbracker
71ef87bc55
testbench workaround for QEMU's SSTATUS XLEN bits
2021-07-23 14:00:44 -04:00
bbracker
3c6a1f8824
replace physical address checking with virtual address checking because address translator is broken
2021-07-21 19:47:13 -04:00
bbracker
d6c93a50aa
fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk
2021-07-20 17:55:44 -04:00
bbracker
945c8d496f
commented out old hack that used hardcoded addresses
2021-07-20 15:03:55 -04:00
bbracker
7694342d4e
ignore mhpmcounters because QEMU doesn't implement them
2021-07-20 13:37:52 -04:00
bbracker
c9775de3b2
testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)
2021-07-20 05:40:39 -04:00
bbracker
5347a58192
major fixes to CSR checking
2021-07-20 00:22:07 -04:00
bbracker
aeaf4a31f0
MemRWM shouldn't factor into PCD checking
2021-07-19 18:03:30 -04:00
bbracker
5911029d2b
make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways
2021-07-19 17:11:42 -04:00
bbracker
009e9d97bf
adapt testbench to removal of ReadDataWEn signal
2021-07-19 15:42:14 -04:00
bbracker
02de6014b2
adapt testbench to removal of signal
2021-07-19 15:41:50 -04:00
bbracker
77b690faf0
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
bbracker
f4f3ef0307
linux testbench progress
2021-07-18 18:47:40 -04:00
bbracker
6feb95c779
swapped out linux testbench signal names
2021-07-17 14:48:12 -04:00
David Harris
c897bef8cd
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
Ben Bracker
9709bd78e1
stop busybear from hanging
2021-07-02 17:22:09 -05:00
bbracker
9927f771cc
linux testbench now ignores HWRITE glitches caused by flush glitches
2021-06-25 09:28:52 -04:00
bbracker
2694a7a43f
made testbench-linux's PCDwrong be FlushD
2021-06-25 08:15:19 -04:00
bbracker
b84419ff4e
overhauled linux testbench and spoofed MTTIME interrupt
2021-06-24 01:42:35 -04:00
David Harris
aef408af58
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
bbracker
665a67f442
linux actually uses FPU now!
2021-06-20 22:29:21 -04:00
bbracker
1f2a967e0f
read from MSTATUS workaround because QEMU has incorrect MSTATUS
2021-06-20 10:11:39 -04:00
bbracker
2611d214a6
testbench update b/c QEMU extends 32b CSRs to 64b
2021-06-20 09:24:19 -04:00
bbracker
9469367da3
make buildroot ignore SSTATUS because QEMU did not originally log it
2021-06-20 05:31:24 -04:00
bbracker
78f4703dc9
MSTATUS workaround
2021-06-20 04:48:09 -04:00
bbracker
927d99cf3b
workaround for ignoring MTIME
2021-06-20 02:26:39 -04:00
bbracker
3e32ba3684
make buildroot waves only turn on after a user-specified point
2021-06-20 00:39:30 -04:00
bbracker
f84a689c19
fixed PCtext error by using blocking assignments
2021-06-18 17:37:40 -04:00
