mirror of
https://github.com/openhwgroup/cvw
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a1c26a16d6
Added back in the csr checking logic. Added code to force timer, external, and software interrupts by using the expected values from qemu's (m/s)cause registers. Still need to prevent wally's timer interrupt.
649 lines
26 KiB
Systemverilog
649 lines
26 KiB
Systemverilog
///////////////////////////////////////////
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// testbench-linux.sv
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//
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// Written: nboorstin@g.hmc.edu 2021
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// Modified:
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//
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// Purpose: Testbench for buildroot or busybear linux
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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`define DEBUG_TRACE 0
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module testbench();
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parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3080000; // # of instructions at which to turn on waves in graphical sim
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parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////// DUT /////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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logic clk, reset;
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logic [`AHBW-1:0] readDataExpected;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] GPIOPinsIn;
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logic [31:0] GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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wallypipelinedsoc dut(.*);
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///////////////////////////////////////////////////////////////////////////////
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//////////////////////// Signals & Shared Macros ///////////////////////////
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//////////////////////// AKA stuff that comes first ///////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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// Sorry if these have gotten decontextualized.
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// Verilog expects them to be defined before they are used.
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// -------------------
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// Signal Declarations
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// -------------------
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// Testbench Core
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integer instrs;
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integer warningCount = 0;
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// PC, Instr Checking
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logic [`XLEN-1:0] PCW;
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integer data_file_all;
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// Write Back stage signals needed for trace compare, but don't actually
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// exist in CPU.
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logic [`XLEN-1:0] MemAdrW, WriteDataW;
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// Write Back trace signals
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logic checkInstrW;
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//integer RegAdr;
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integer fault;
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logic TrapW;
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// Signals used to parse the trace file.
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logic checkInstrM;
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integer matchCount;
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string line;
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logic [`XLEN-1:0] ExpectedPCM;
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logic [31:0] ExpectedInstrM;
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string textM;
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string token;
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string ExpectedTokens [31:0];
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integer index;
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integer StartIndex, EndIndex;
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integer TokenIndex;
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integer MarkerIndex;
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integer NumCSRM;
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// Memory stage expected values from trace
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string RegWriteM;
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integer ExpectedRegAdrM;
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logic [`XLEN-1:0] ExpectedRegValueM;
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string MemOpM;
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logic [`XLEN-1:0] ExpectedMemAdrM, ExpectedMemReadDataM, ExpectedMemWriteDataM;
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string ExpectedCSRArrayM[integer];
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logic [`XLEN-1:0] ExpectedCSRArrayValueM[integer];
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// Write back stage expected values from trace
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logic [`XLEN-1:0] ExpectedPCW;
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logic [31:0] ExpectedInstrW;
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string textW;
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string RegWriteW;
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integer ExpectedRegAdrW;
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logic [`XLEN-1:0] ExpectedRegValueW;
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string MemOpW;
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logic [`XLEN-1:0] ExpectedMemAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
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integer NumCSRW;
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string ExpectedCSRArrayW[integer];
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logic [`XLEN-1:0] ExpectedCSRArrayValueW[integer];
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logic [`XLEN-1:0] ExpectedIntType;
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integer NumCSRMIndex;
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integer NumCSRWIndex;
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integer NumCSRPostWIndex;
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// -----------
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// Error Macro
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// -----------
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`define ERROR \
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$display("processed %0d instructions with %0d warnings", instrs, warningCount); \
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$stop;
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initial begin
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data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
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end
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assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.StallM;
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// trapW will already be invalid in there was an InstrPageFault in the previous instruction.
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assign checkInstrW = dut.hart.ieu.InstrValidW & ~dut.hart.StallW;
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flopenrc #(`XLEN) MemAdrWReg(clk, reset, dut.hart.FlushW, ~dut.hart.StallW, dut.hart.ieu.dp.MemAdrM, MemAdrW);
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flopenrc #(`XLEN) WriteDataWReg(clk, reset, dut.hart.FlushW, ~dut.hart.StallW, dut.hart.WriteDataM, WriteDataW);
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flopenrc #(`XLEN) PCWReg(clk, reset, dut.hart.FlushW, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
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flopenr #(1) TrapWReg(clk, reset, ~dut.hart.StallW, dut.hart.hzu.TrapM, TrapW);
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// because qemu does not match exactly to wally it is necessary to read the the
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// trace in the memory stage and detect if anything in wally must be overwritten.
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// This includes mtimer, interrupts, and various bits in mstatus and xtval.
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// then on the next posedge the expected state is registered.
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// on the next falling edge the expected state is compared to the wally state.
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// step 0: read the expected state
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always @(negedge clk) begin
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// always check PC, instruction bits
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if (checkInstrM) begin
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// read 1 line of the trace file
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matchCount = $fgets(line, data_file_all);
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if(`DEBUG_TRACE > 0) $display("Time %t, line %x", $time, line);
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matchCount = $sscanf(line, "%x %x %s", ExpectedPCM, ExpectedInstrM, textM);
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//$display("matchCount %d, PCM %x ExpectedInstrM %x textM %x", matchCount, ExpectedPCM, ExpectedInstrM, textM);
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// for the life of me I cannot get any build in C or C++ string parsing functions/methods to work.
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// strtok was the best idea but it cannot be used correctly as system verilog does not have null
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// terminated strings.
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// Just going to do this char by char.
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StartIndex = 0;
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TokenIndex = 0;
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//$display("len = %d", line.len());
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for(index = 0; index < line.len(); index++) begin
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//$display("char = %s", line[index]);
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if (line[index] == " " || line[index] == "\n") begin
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EndIndex = index;
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ExpectedTokens[TokenIndex] = line.substr(StartIndex, EndIndex-1);
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//$display("In Tokenizer %s", line.substr(StartIndex, EndIndex-1));
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StartIndex = EndIndex + 1;
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TokenIndex++;
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end
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end
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MarkerIndex = 3;
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NumCSRM = 0;
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MemOpM = "";
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RegWriteM = "";
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#2;
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while(TokenIndex > MarkerIndex) begin
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// parse the GPR
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if (ExpectedTokens[MarkerIndex] == "GPR") begin
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RegWriteM = ExpectedTokens[MarkerIndex];
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%d", ExpectedRegAdrM);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedRegValueM);
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MarkerIndex += 3;
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// parse memory address, read data, and/or write data
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end else if(ExpectedTokens[MarkerIndex].substr(0, 2) == "Mem") begin
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MemOpM = ExpectedTokens[MarkerIndex];
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedMemAdrM);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+2], "%x", ExpectedMemWriteDataM);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+3], "%x", ExpectedMemReadDataM);
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MarkerIndex += 4;
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// parse CSRs
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end else if(ExpectedTokens[MarkerIndex] == "CSR" || NumCSRM > 0) begin
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MarkerIndex++;
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matchCount = $sscanf(ExpectedTokens[MarkerIndex], "%s", ExpectedCSRArrayM[NumCSRM]);
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matchCount = $sscanf(ExpectedTokens[MarkerIndex+1], "%x", ExpectedCSRArrayValueM[NumCSRM]);
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// if we get an xcause with the interrupt bit set we must generate an interrupt as interrupts
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// are imprecise. Forcing the trap at this time will allow wally to track what qemu does.
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// the msb of xcause will be set.
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// bits 1:0 select mode; 0 = user, 1 = superviser, 3 = machine
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// bits 3:2 select the type of interrupt, 0 = software, 1 = timer, 2 = external
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if(ExpectedCSRArrayM[NumCSRM].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRM][`XLEN-1] == 1'b1)) begin
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//what type?
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ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C;
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$display("%t: CSR = %s. Forcing interrupt of cause = %x", $time, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]);
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if(ExpectedIntType == 0) begin
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force dut.hart.priv.SwIntM = 1'b1;
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$display("Force SwIntM");
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end
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else if(ExpectedIntType == 4) begin
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force dut.hart.priv.TimerIntM = 1'b1;
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$display("Force TimeIntM");
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end
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else if(ExpectedIntType == 8) begin
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force dut.hart.priv.ExtIntM = 1'b1;
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$display("Force ExtIntM");
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end
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end
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NumCSRM++;
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end
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end
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// override on special conditions
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if (ExpectedMemAdrM == 'h10000005) begin
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//$display("%t: Overwriting read data from CLINT.", $time);
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force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM;
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end
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if(textM.substr(0,5) == "rdtime") begin
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$display("%t: Overwrite read value of CSR on read of MTIME in memory stage.", $time);
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force dut.hart.priv.csr.CSRReadValM = ExpectedRegValueM;
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//dut.hart.ieu.dp.regf.wd3
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end
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end // if (checkInstrM)
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end
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// step 1: register expected state into the write back stage.
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always @(posedge clk) begin
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if (reset) begin
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ExpectedPCW <= '0;
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ExpectedInstrW <= '0;
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textW <= "";
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RegWriteW <= "";
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ExpectedRegAdrW <= '0;
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ExpectedRegValueW <= '0;
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ExpectedMemAdrW <= '0;
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MemOpW <= "";
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ExpectedMemWriteDataW <= '0;
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ExpectedMemReadDataW <= '0;
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NumCSRW <= '0;
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end
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else if(~dut.hart.StallW) begin
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if(dut.hart.FlushW) begin
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ExpectedPCW <= '0;
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ExpectedInstrW <= '0;
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textW <= "";
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RegWriteW <= "";
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ExpectedRegAdrW <= '0;
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ExpectedRegValueW <= '0;
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ExpectedMemAdrW <= '0;
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MemOpW <= "";
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ExpectedMemWriteDataW <= '0;
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ExpectedMemReadDataW <= '0;
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NumCSRW <= '0;
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end else begin
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ExpectedPCW <= ExpectedPCM;
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ExpectedInstrW <= ExpectedInstrM;
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textW <= textM;
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RegWriteW <= RegWriteM;
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ExpectedRegAdrW <= ExpectedRegAdrM;
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ExpectedRegValueW <= ExpectedRegValueM;
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ExpectedMemAdrW <= ExpectedMemAdrM;
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MemOpW <= MemOpM;
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ExpectedMemWriteDataW <= ExpectedMemWriteDataM;
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ExpectedMemReadDataW <= ExpectedMemReadDataM;
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NumCSRW <= NumCSRM;
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for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRW; NumCSRWIndex++) begin
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ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex];
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ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex];
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end
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end
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// override on special conditions
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#1;
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if(textW.substr(0,5) == "rdtime") begin
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$display("%t:Releasing force of CSRReadValM.", $time);
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release dut.hart.priv.csr.CSRReadValM;
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//release dut.hart.ieu.dp.regf.wd3;
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end
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if (ExpectedMemAdrM == 'h10000005) begin
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//$display("%t: releasing force of ReadDataM.", $time);
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release dut.hart.ieu.dp.ReadDataM;
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end
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// remove forces on interrupts
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for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin
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if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin
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//what type?
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$display("$t: Releasing all forces on interrupts", $time);
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release dut.hart.priv.SwIntM;
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release dut.hart.priv.TimerIntM;
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release dut.hart.priv.ExtIntM;
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end
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end
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end
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end
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// step2: make all checks in the write back stage.
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always @(negedge clk) begin
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// always check PC, instruction bits
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if (checkInstrW) begin
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// check PCW
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fault = 0;
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if(PCW != ExpectedPCW) begin
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$display("PCW: %016x does not equal ExpectedPCW: %016x", PCW, ExpectedPCW);
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fault = 1;
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end
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// check instruction value
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if(dut.hart.ifu.InstrW != ExpectedInstrW) begin
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$display("InstrW: %x does not equal ExpectedInstrW: %x", dut.hart.ifu.InstrW, ExpectedInstrW);
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fault = 1;
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end
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#2; // delay 2 ns.
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if(`DEBUG_TRACE > 1) begin
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$display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
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$display("RF[%02d]: %016x ? expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
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end
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if (RegWriteW == "GPR") begin
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if (dut.hart.ieu.dp.regf.a3 != ExpectedRegAdrW) begin
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$display("Reg Write Address: %02d does not equal expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
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fault = 1;
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end
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if (dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW] != ExpectedRegValueW) begin
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$display("RF[%02d]: %016x does not equal expected value: %016x", ExpectedRegAdrW, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW);
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fault = 1;
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end
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end
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if (MemOpW.substr(0,2) == "Mem") begin
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if(`DEBUG_TRACE > 2) $display("\tMemAdrW: %016x ? expected: %016x", MemAdrW, ExpectedMemAdrW);
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// always check address
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if (MemAdrW != ExpectedMemAdrW) begin
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$display("MemAdrW: %016x does not equal expected value: %016x", MemAdrW, ExpectedMemAdrW);
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fault = 1;
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end
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// check read data
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if(MemOpW == "MemR" || MemOpW == "MemRW") begin
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if(`DEBUG_TRACE > 2) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
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if (dut.hart.ieu.dp.ReadDataW != ExpectedMemReadDataW) begin
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$display("ReadDataW: %016x does not equal expected value: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
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fault = 1;
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end
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/* -----\/----- EXCLUDED -----\/-----
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if (ExpectedMemAdr == 'h10000005) begin
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force dut.hart.ieu.dp.ReadDataW = ExpectedMemReadData;
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force dut.hart.ieu.dp.regf.wd3 = RegValue;
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end else begin
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end
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-----/\----- EXCLUDED -----/\----- */
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end
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// check write data
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else if(ExpectedTokens[MarkerIndex] == "MemW" || ExpectedTokens[MarkerIndex] == "MemRW") begin
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if(`DEBUG_TRACE > 2) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW);
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if (WriteDataW != ExpectedMemWriteDataW) begin
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$display("WriteDataW: %016x does not equal expected value: %016x", WriteDataW, ExpectedMemWriteDataW);
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fault = 1;
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end
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end
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// check csr
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for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin
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case(ExpectedCSRArrayW[NumCSRPostWIndex])
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"mhartid": begin
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if(`DEBUG_TRACE > 3) begin
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$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
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end
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if (dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
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$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
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fault = 1;
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end
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end
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"mstatus": begin
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if(`DEBUG_TRACE > 3) begin
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$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
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end
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if ((dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW) != (ExpectedCSRArrayValueW[NumCSRPostWIndex])) begin
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$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
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fault = 1;
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end
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end
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"mtvec": begin
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if(`DEBUG_TRACE > 3) begin
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$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
end
|
|
if (dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
|
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
fault = 1;
|
|
end
|
|
end
|
|
"mip": begin
|
|
if(`DEBUG_TRACE > 3) begin
|
|
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
end
|
|
if (dut.hart.priv.csr.genblk1.csrm.MIP_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
|
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIP_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
fault = 1;
|
|
end
|
|
end
|
|
"mie": begin
|
|
if(`DEBUG_TRACE > 3) begin
|
|
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
end
|
|
if (dut.hart.priv.csr.genblk1.csrm.MIE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
|
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
fault = 1;
|
|
end
|
|
end
|
|
"mideleg": begin
|
|
if(`DEBUG_TRACE > 3) begin
|
|
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
end
|
|
if (dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
|
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
fault = 1;
|
|
end
|
|
end
|
|
"medeleg": begin
|
|
if(`DEBUG_TRACE > 3) begin
|
|
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
end
|
|
if (dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
|
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
fault = 1;
|
|
end
|
|
end
|
|
"mepc": begin
|
|
if(`DEBUG_TRACE > 3) begin
|
|
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
end
|
|
if (dut.hart.priv.csr.genblk1.csrm.MEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
|
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
fault = 1;
|
|
end
|
|
end
|
|
"mtval": begin
|
|
if(`DEBUG_TRACE > 3) begin
|
|
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
end
|
|
if (dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
|
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
fault = 1;
|
|
end
|
|
end
|
|
|
|
"sepc": begin
|
|
if(`DEBUG_TRACE > 3) begin
|
|
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
end
|
|
if (dut.hart.priv.csr.genblk1.csrs.SEPC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
|
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
fault = 1;
|
|
end
|
|
end
|
|
"scause": begin
|
|
if(`DEBUG_TRACE > 3) begin
|
|
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
end
|
|
if (dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
|
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
fault = 1;
|
|
end
|
|
end
|
|
"stvec": begin
|
|
if(`DEBUG_TRACE > 3) begin
|
|
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
end
|
|
if (dut.hart.priv.csr.genblk1.csrs.STVEC_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
|
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.STVEC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
fault = 1;
|
|
end
|
|
end
|
|
"stval": begin
|
|
if(`DEBUG_TRACE > 3) begin
|
|
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
end
|
|
if (dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin
|
|
$display("CSR: %s = %016x, does not equal expected value %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
|
|
fault = 1;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
|
|
end
|
|
if (fault == 1) begin
|
|
`ERROR
|
|
end
|
|
end // if (checkInstrW)
|
|
end // always @ (negedge clk)
|
|
|
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
//////////////////////////////// Testbench Core ///////////////////////////////
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
// --------------
|
|
// Initialization
|
|
// --------------
|
|
initial
|
|
begin
|
|
instrs = 0;
|
|
reset <= 1; # 22; reset <= 0;
|
|
end
|
|
// initial loading of memories
|
|
initial begin
|
|
$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
|
|
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
|
|
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
|
|
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
|
|
end
|
|
|
|
// -------
|
|
// Running
|
|
// -------
|
|
always
|
|
begin
|
|
clk <= 1; # 5; clk <= 0; # 5;
|
|
end
|
|
|
|
|
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
///////////////////////////////// Miscellaneous ///////////////////////////////
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
// Instr Opcode Tracking
|
|
// For waveview convenience
|
|
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
|
logic [31:0] InstrW;
|
|
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
|
|
dut.hart.ifu.icache.controller.FinalInstrRawF,
|
|
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
|
|
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
|
|
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
|
|
|
// ------------------
|
|
// Address Translator
|
|
// ------------------
|
|
/**
|
|
* Walk the page table stored in dtim according to sv39 logic and translate a
|
|
* virtual address to a physical address.
|
|
*
|
|
* See section 4.3.2 of the RISC-V Privileged specification for a full
|
|
* explanation of the below algorithm.
|
|
*/
|
|
logic SvMode, PTE_R, PTE_X;
|
|
logic [`XLEN-1:0] SATP, PTE;
|
|
logic [55:0] BaseAdr, PAdr;
|
|
logic [8:0] VPN [2:0];
|
|
logic [11:0] Offset;
|
|
function logic [`XLEN-1:0] adrTranslator(
|
|
input logic [`XLEN-1:0] adrIn);
|
|
begin
|
|
int i;
|
|
// Grab the SATP register from privileged unit
|
|
SATP = dut.hart.priv.csr.SATP_REGW;
|
|
// Split the virtual address into page number segments and offset
|
|
VPN[2] = adrIn[38:30];
|
|
VPN[1] = adrIn[29:21];
|
|
VPN[0] = adrIn[20:12];
|
|
Offset = adrIn[11:0];
|
|
// We do not support sv48; only sv39
|
|
SvMode = SATP[63];
|
|
// Only perform translation if translation is on and the processor is not
|
|
// in machine mode
|
|
if (SvMode && (dut.hart.priv.PrivilegeModeW != `M_MODE)) begin
|
|
BaseAdr = SATP[43:0] << 12;
|
|
for (i = 2; i >= 0; i--) begin
|
|
PAdr = BaseAdr + (VPN[i] << 3);
|
|
// dtim.RAM is 64-bit addressed. PAdr specifies a byte. We right shift
|
|
// by 3 (the PTE size) to get the requested 64-bit PTE.
|
|
PTE = dut.uncore.dtim.RAM[PAdr >> 3];
|
|
PTE_R = PTE[1];
|
|
PTE_X = PTE[3];
|
|
if (PTE_R || PTE_X) begin
|
|
// Leaf page found
|
|
break;
|
|
end else begin
|
|
// Go to next level of table
|
|
BaseAdr = PTE[53:10] << 12;
|
|
end
|
|
end
|
|
// Determine which parts of the PTE page number to use based on the
|
|
// level of the page table we reached.
|
|
if (i == 2) begin
|
|
// Gigapage
|
|
assign adrTranslator = {8'b0, PTE[53:28], VPN[1], VPN[0], Offset};
|
|
end else if (i == 1) begin
|
|
// Megapage
|
|
assign adrTranslator = {8'b0, PTE[53:19], VPN[0], Offset};
|
|
end else begin
|
|
// Kilopage
|
|
assign adrTranslator = {8'b0, PTE[53:10], Offset};
|
|
end
|
|
end else begin
|
|
// Direct translation if address translation is not on
|
|
assign adrTranslator = adrIn;
|
|
end
|
|
end
|
|
endfunction
|
|
endmodule
|
|
|